| Rev |
Log message |
Author |
Age |
Path |
| 93 |
Initial revision, memory image for skipjack test. |
rehayes |
4574d 12h |
/ |
| 92 |
Add sync reset to bypass register. |
rehayes |
4574d 12h |
/ |
| 91 |
Update to use one ISR to handle all 127 interrupts. |
rehayes |
4574d 12h |
/ |
| 90 |
Cosmetic omment changes. |
rehayes |
4574d 13h |
/ |
| 89 |
Code cleanup. |
rehayes |
4588d 11h |
/ |
| 88 |
Updated with complete code |
rehayes |
4661d 20h |
/ |
| 87 |
First pass JTAG TAP, state machine working but needs work to complete reset of TAP. |
rehayes |
4788d 11h |
/ |
| 86 |
Add JTAG test tasks |
rehayes |
4788d 11h |
/ |
| 85 |
Corrections to instruction set details example code, added test bench debugger. |
rehayes |
5062d 20h |
/ |
| 84 |
Added notes on SKIPJACK encrypt/decrypt applications, testbench debugger and user guide corrections. |
rehayes |
5062d 20h |
/ |
| 83 |
Add subroutine quailifier. |
rehayes |
5062d 20h |
/ |
| 82 |
Added debug module to assist in software debugging. |
rehayes |
5063d 14h |
/ |
| 81 |
Initial checkin of the SKIPJACK encrypt/decrypt application program |
rehayes |
5063d 15h |
/ |
| 80 |
Added IRQ bypass registers and Test bench appendix |
rehayes |
5125d 16h |
/ |
| 79 |
Added IRQ bypass registers and Test bench appendix |
rehayes |
5125d 16h |
/ |
| 78 |
Added IRQ bypass registers and Test bench appendix |
rehayes |
5125d 16h |
/ |
| 77 |
Documentation update |
rehayes |
5125d 16h |
/ |
| 76 |
Updated xgate_risc.v for xlink synthesis warnings. |
rehayes |
5148d 17h |
/ |
| 75 |
Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382 |
rehayes |
5148d 17h |
/ |
| 74 |
Code cleanup, eliminated index 0 of input and output interrupts. |
rehayes |
5153d 18h |
/ |
| 73 |
Code cleanup, eliminated index 0 of input and output interrupts. |
rehayes |
5153d 18h |
/ |
| 72 |
Code cleanup, eliminated index 0 of input and output interrupts. |
rehayes |
5153d 18h |
/ |
| 71 |
Added irq bypass registers to rtl, testbench and doc. |
rehayes |
5154d 21h |
/ |
| 70 |
Updated with interrupt bypass controll registers. |
rehayes |
5154d 21h |
/ |
| 69 |
New test to verify irq interrupt priority encoder. |
rehayes |
5154d 21h |
/ |
| 68 |
Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. |
rehayes |
5154d 21h |
/ |
| 67 |
Added irq bypass function and controll registers. Made lowest interrupt index highest priority. |
rehayes |
5154d 21h |
/ |
| 66 |
Fix testbench and RISC core related to debug mode and wait states. |
rehayes |
5174d 17h |
/ |
| 65 |
Parameterize delays based on number of RAM wait states. |
rehayes |
5174d 17h |
/ |
| 64 |
Fixed more bugs related to wait states and debug mode. |
rehayes |
5174d 17h |
/ |
