Rev |
Log message |
Author |
Age |
Path |
35 |
Updates the memory testing program to work successfully with the Gnu build
tools--particularly the GNU C-preprocessor from GCC and the GNU assembler from
Binutils. |
dgisselq |
3104d 15h |
/ |
34 |
Bug fix: This sets as a positive voltage bias (not negative) the maximum
value of 0x07fff, where as the negative maximum value of 0x08000 properly
(now) reflects nearly ground--as one would desire. (Last time around I had
these backwards.) |
dgisselq |
3108d 10h |
/ |
33 |
Oops -- the audio was wired audio first then the interrupt controller, not
the other way around. This adjusts regdefs to match what's on the chip. |
dgisselq |
3108d 11h |
/ |
32 |
Just noticed that the timer was fixed on this. This change adjusts the
timer to support audio at a user selectable rate. |
dgisselq |
3108d 11h |
/ |
31 |
A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25. |
dgisselq |
3108d 12h |
/ |
30 |
Bug fixes. In particular, this fixes a segmentation violation. |
dgisselq |
3108d 16h |
/ |
29 |
This adds a vastly updated and superious ziprun capability to the repository.
ziprun now accepts ELF program files *only*, reads them, and places them onto
the board. This includes the ability, within the ELF file, of specifying
whether or not the data is sent to block ram, SD ram, or Flash, as well as
the ability of specifying the initial address. (Of course, that's a one time
thing--to always have the same initial address, set the address in
rtl/busmaster.v) |
dgisselq |
3109d 08h |
/ |
28 |
Oops--two files needed by zipdbg weren't originally placed in the directory. |
dgisselq |
3109d 12h |
/ |
27 |
Bug fix: the last_state register now correctly reflects all 5-bits of the state
machine. (Useful when detecting lockups ...) |
dgisselq |
3109d 13h |
/ |
26 |
Some bug fixes, and the long jump early branching integration. |
dgisselq |
3109d 13h |
/ |
25 |
Fixing compile time warnings. |
dgisselq |
3109d 13h |
/ |
24 |
Added the #define necessary to enable (and clear) SCOPE interrupts. |
dgisselq |
3115d 11h |
/ |
23 |
This fixes a bug in the early branching system, and clarifies that early
branch instructions will not affect the flags. It's a basic bug fix update. |
dgisselq |
3117d 22h |
/ |
22 |
Added the mkdatev.pl file. (Oops!) |
dgisselq |
3120d 15h |
/ |
21 |
Files, not links, to replace what were once broken links in this project. |
dgisselq |
3170d 22h |
/ |
20 |
Documents, borrowed from their source projects, and reproduced here. These
describe the various components of the board. |
dgisselq |
3170d 22h |
/ |
19 |
Step one in fixing soft link poblems. The following files were soft links,
and not brought into the svn repository properly. They'll be replaced in the
next update with their full sources. |
dgisselq |
3170d 22h |
/ |
18 |
Got the bitfile back up to speed at 80 MHz. |
dgisselq |
3174d 12h |
/ |
17 |
Some basic updates, to include adding in a missing file (zipstate). Most of
these updates include making sure that the XuLA2 device can be accessed via
the USB. (Prior versions accessed the FPGA via serial port or network ...) |
dgisselq |
3174d 12h |
/ |
16 |
Updates to allow a test of the ICAP configuration interface. |
dgisselq |
3174d 12h |
/ |
15 |
WORKING VERSION! ... or, at least the memory test works. |
dgisselq |
3176d 08h |
/ |
14 |
Quick bug fix. |
dgisselq |
3176d 08h |
/ |
13 |
This version is now working. (It probably would've worked before, but
everything is now working.) |
dgisselq |
3176d 08h |
/ |
12 |
Modified to match the settings I'm now using within ISE. |
dgisselq |
3176d 11h |
/ |
11 |
Getting software up and running on the board for the first time. (Not there
yet, but I think these items have now proven themselves.) |
dgisselq |
3176d 11h |
/ |
10 |
Changed the name of the memtest.s file. |
dgisselq |
3176d 11h |
/ |
9 |
Bug fixes, optimizations, etc. as part of building for an actual hardware
implementation. Most notably, the speed was lowered from 80MHz down to
76 MHz. |
dgisselq |
3176d 11h |
/ |
8 |
Added an interface description to the comments at the top of the file. |
dgisselq |
3178d 20h |
/ |
7 |
Mostly minor changes. Fixed the legal copyright statement in the UART files,
adjusted some comments, and made sure that the zipdbg program contained all
the latest features from our Vault. |
dgisselq |
3178d 21h |
/ |
6 |
Initial file load, likely to be buggy, but the initial load nonetheless. |
dgisselq |
3179d 07h |
/ |