| Rev |
Log message |
Author |
Age |
Path |
| 76 |
Now tries to avoid reading from the stack if the stack addresses are already
known to be bad. That way, the debugger tries to preserve any bus error address
already on the buserr device. |
dgisselq |
2934d 03h |
/ |
| 75 |
Added simulation capability for the SD-Card, as well as debugging output for the
DMA. (The SD-Card debug may not be fully featured, yet, but it has gotten me
to where I can talk to the card.) |
dgisselq |
2934d 04h |
/ |
| 74 |
Adds the SD-card capability, and connects the debug wires to/from the uartdev
in case it needs to be debugged. |
dgisselq |
2934d 04h |
/ |
| 73 |
Simplified logic. |
dgisselq |
2934d 04h |
/ |
| 72 |
Sets XULA25 as the default. |
dgisselq |
2934d 04h |
/ |
| 71 |
Needed to play with subtle timing to get this to build. Expect me to play
with these two clock numbers more. |
dgisselq |
2934d 04h |
/ |
| 70 |
Cosmetic (minor) update. |
dgisselq |
2934d 04h |
/ |
| 69 |
Massive logic simplification. This is also the first (verified) working
version. |
dgisselq |
2934d 04h |
/ |
| 68 |
Fixes the debug ack line, so it no longer acks when there isn't a dbg_stb.
Fixed the multiply option parameter, so it sets a 3-clock multiply properly.
Adjusted the watchdog timer so that it now produces a timer that doesn't
reload--since this is pointless for a watchdog. Finally, connects a reset
line to the DMA, to make certain that resetting the CPU will also reset any
ongoing DMA operation. |
dgisselq |
2934d 04h |
/ |
| 67 |
Simplifies logic, and guarantees that the minimum set value will always
produce an int. For example, if the count was X before, setting X-1 wouldn't
produce an interrupt since it had passed. Now it produces an interrupt, and
keeps the next interrupt valid. |
dgisselq |
2934d 04h |
/ |
| 66 |
Simplified logic (barely). |
dgisselq |
2934d 04h |
/ |
| 65 |
Makes the auto-reload feature a parameterized (generic) feature, so the same
code will work for both auto-reloadable and non-autoreloadable (i.e. watchdog)
timers. |
dgisselq |
2934d 04h |
/ |
| 64 |
First (verified) working version. |
dgisselq |
2934d 04h |
/ |
| 63 |
Simplified logic. |
dgisselq |
2934d 04h |
/ |
| 62 |
Removed the pipe logic from the non-pipelined version, and made the NOOP a
specific ALU instruction so that the PC is always properly updated. |
dgisselq |
2934d 04h |
/ |
| 61 |
Fixed the timing control wires: busy and valid will never both be true. Busy
will be true (now) until valid is asserted, and busy will never not be
asserted until valid is true. |
dgisselq |
2934d 04h |
/ |
| 60 |
LONG_MPY upgrade. This is part of swapping out the LDIHI instruction for a
MPY, and the MPYS and MPYU instructions for MPYSHI and MPYUHI respectively. |
dgisselq |
2934d 04h |
/ |
| 59 |
Simplified logic. |
dgisselq |
2934d 04h |
/ |
| 58 |
Bug fix: the UART can now be reconfigured post-boot without a BREAK condition. |
dgisselq |
2934d 05h |
/ |
| 57 |
Fixed the TX/RX addresses so that they match the documentation: TX first, then
RX. |
dgisselq |
2942d 04h |
/ |
| 56 |
Brings code in line with the OpenCores core: parameterizes the reload value,
and the number of bits in the timer. |
dgisselq |
2942d 04h |
/ |
| 55 |
Updated copyright notice. |
dgisselq |
2942d 04h |
/ |
| 54 |
Updated copyright notice. |
dgisselq |
2942d 04h |
/ |
| 53 |
Added a touch of error checking. |
dgisselq |
2982d 05h |
/ |
| 52 |
This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change. |
dgisselq |
2982d 05h |
/ |
| 51 |
Lots of bug fixes. The ugliest were in the prefetch cache, where instructions
from one cache line were being issued as valid in another. Other fixes include
pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the
decode was adjusted so that brev no longer affects the flags. |
dgisselq |
2992d 03h |
/ |
| 50 |
Updates to fix some broken early branching code, both in idecode and pfcache. |
dgisselq |
3001d 06h |
/ |
| 49 |
Added some documentation to make the read and write calls easier to understand. |
dgisselq |
3010d 06h |
/ |
| 48 |
Cleaned up the documentation a touch. It no longer reads like the bugs I used
to debug are still being debugged ... |
dgisselq |
3012d 07h |
/ |
| 47 |
Fixes the "NAN" clocks/second output, as well as making input timing come closer
to a realistic timing. (I actually don't know what timing the JTAG port is
providing, but ... the new timer is closer.) |
dgisselq |
3012d 08h |
/ |
