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Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] - Rev 141

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Rev	Log message	Author	Age	Path
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7722d 01h	/8051/tags/rel_1/
140	cahnge assigment to pc_wait (remove istb_o)	simont	7722d 01h	/8051/tags/rel_1/
139	add aditional alu destination to solve critical path.	simont	7722d 19h	/8051/tags/rel_1/
138	Change buffering to save one clock per instruction.	simont	7722d 19h	/8051/tags/rel_1/
137	change to fit xrom.	simont	7723d 00h	/8051/tags/rel_1/
136	registering outputs.	simont	7723d 00h	/8051/tags/rel_1/
135	prepared start of receiving if ren is not active.	simont	7729d 00h	/8051/tags/rel_1/
134	fix bug in case execution of two data dependent instructions.	simont	7729d 00h	/8051/tags/rel_1/
133	fix bug in substraction.	simont	7729d 02h	/8051/tags/rel_1/
132	change branch instruction execution (reduse needed clock periods).	simont	7732d 18h	/8051/tags/rel_1/
131	prepare programs for new timing.	simont	7732d 18h	/8051/tags/rel_1/
130	prepared programs for new timing.	simont	7732d 18h	/8051/tags/rel_1/
129	updated...	simont	7732d 18h	/8051/tags/rel_1/
128	chance idat_ir to 24 bit wide	simont	7742d 01h	/8051/tags/rel_1/
127	fix bug (cyc_o and stb_o)	simont	7742d 01h	/8051/tags/rel_1/
126	define OC8051_XILINX_RAMB added	simont	7742d 01h	/8051/tags/rel_1/
125	update, add prescaler, rclk, tclk.	simont	7742d 01h	/8051/tags/rel_1/
124	add support for external rom from xilinx ramb4	simont	7742d 01h	/8051/tags/rel_1/
123	fiz bug iv pcs operation.	simont	7743d 21h	/8051/tags/rel_1/
122	deifne OC8051_ROM added	simont	7747d 01h	/8051/tags/rel_1/
121	Change pc add value from 23'h to 16'h	simont	7747d 01h	/8051/tags/rel_1/
120	defines for pherypherals added	simont	7747d 22h	/8051/tags/rel_1/
119	remove signal sbuf_txd [12:11]	simont	7748d 02h	/8051/tags/rel_1/
118	change wr_sft to 2 bit wire.	simont	7748d 19h	/8051/tags/rel_1/
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7748d 19h	/8051/tags/rel_1/
116	change sfr's interface.	simont	7750d 20h	/8051/tags/rel_1/
115	change uart to meet timing.	simont	7750d 22h	/8051/tags/rel_1/
114	remove t2mod register	simont	7754d 00h	/8051/tags/rel_1/
113	signal prsc_ow added.	simont	7754d 00h	/8051/tags/rel_1/
112	change timers to meet timing specifications (add divider with 12)	simont	7754d 00h	/8051/tags/rel_1/

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Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] - Rev 141

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