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[/] [8051/] [tags/] [rel_1/] - Rev 147

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Rev	Log message	Author	Age	Path
147	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7807d 12h	/8051/tags/rel_1/
146	fix bug in movc intruction.	simont	7807d 12h	/8051/tags/rel_1/
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7812d 15h	/8051/tags/rel_1/
144	chsnge comp.des to des1	simont	7812d 16h	/8051/tags/rel_1/
143	add wire sub_result, conect it to des_acc and des1.	simont	7812d 16h	/8051/tags/rel_1/
142	optimize state machine.	simont	7813d 17h	/8051/tags/rel_1/
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7813d 18h	/8051/tags/rel_1/
140	cahnge assigment to pc_wait (remove istb_o)	simont	7813d 18h	/8051/tags/rel_1/
139	add aditional alu destination to solve critical path.	simont	7814d 12h	/8051/tags/rel_1/
138	Change buffering to save one clock per instruction.	simont	7814d 12h	/8051/tags/rel_1/
137	change to fit xrom.	simont	7814d 18h	/8051/tags/rel_1/
136	registering outputs.	simont	7814d 18h	/8051/tags/rel_1/
135	prepared start of receiving if ren is not active.	simont	7820d 17h	/8051/tags/rel_1/
134	fix bug in case execution of two data dependent instructions.	simont	7820d 17h	/8051/tags/rel_1/
133	fix bug in substraction.	simont	7820d 20h	/8051/tags/rel_1/
132	change branch instruction execution (reduse needed clock periods).	simont	7824d 11h	/8051/tags/rel_1/
131	prepare programs for new timing.	simont	7824d 11h	/8051/tags/rel_1/
130	prepared programs for new timing.	simont	7824d 11h	/8051/tags/rel_1/
129	updated...	simont	7824d 11h	/8051/tags/rel_1/
128	chance idat_ir to 24 bit wide	simont	7833d 18h	/8051/tags/rel_1/
127	fix bug (cyc_o and stb_o)	simont	7833d 18h	/8051/tags/rel_1/
126	define OC8051_XILINX_RAMB added	simont	7833d 18h	/8051/tags/rel_1/
125	update, add prescaler, rclk, tclk.	simont	7833d 18h	/8051/tags/rel_1/
124	add support for external rom from xilinx ramb4	simont	7833d 18h	/8051/tags/rel_1/
123	fiz bug iv pcs operation.	simont	7835d 14h	/8051/tags/rel_1/
122	deifne OC8051_ROM added	simont	7838d 18h	/8051/tags/rel_1/
121	Change pc add value from 23'h to 16'h	simont	7838d 18h	/8051/tags/rel_1/
120	defines for pherypherals added	simont	7839d 15h	/8051/tags/rel_1/
119	remove signal sbuf_txd [12:11]	simont	7839d 19h	/8051/tags/rel_1/
118	change wr_sft to 2 bit wire.	simont	7840d 12h	/8051/tags/rel_1/

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[/] [8051/] [tags/] [rel_1/] - Rev 147

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