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Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] - Rev 38

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Rev Log message Author Age Path
38 fix some bugs simont 7971d 13h /8051/tags/rel_1/
37 added signals ack, stb and cyc simont 7971d 14h /8051/tags/rel_1/
36 fix bugs in mode 0 simont 7971d 14h /8051/tags/rel_1/
35 design docunemt simont 7972d 12h /8051/tags/rel_1/
34 specification docunemt simont 7972d 12h /8051/tags/rel_1/
33 fix some bugs simont 7972d 18h /8051/tags/rel_1/
32 overflow repaired simont 7972d 18h /8051/tags/rel_1/
31 fix some bugs simont 7979d 10h /8051/tags/rel_1/
30 mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32 simont 7982d 17h /8051/tags/rel_1/
29 fix some bugs simont 7982d 18h /8051/tags/rel_1/
28 remove syn signal simont 7982d 18h /8051/tags/rel_1/
27 fix some bugs simont 7982d 18h /8051/tags/rel_1/
26 main divider logic was optimized not optimized by compiler, so I did it by hand markom 7982d 20h /8051/tags/rel_1/
25 divider and multiplier pass test markom 7983d 14h /8051/tags/rel_1/
24 intensively tests all instructions markom 7983d 19h /8051/tags/rel_1/
23 mul & div use 4 clocks simont 7984d 09h /8051/tags/rel_1/
22 fix some bugs simont 7984d 10h /8051/tags/rel_1/
21 mul bug fixed markom 7984d 15h /8051/tags/rel_1/
20 multiplier and divider changed so they complete in 4 cycles markom 7984d 17h /8051/tags/rel_1/
19 combinatorial loop removed simont 7985d 10h /8051/tags/rel_1/
18 rst signal added simont 7988d 15h /8051/tags/rel_1/
17 fix some bugs simont 7988d 15h /8051/tags/rel_1/
16 inputs ram and op2 removed simont 7988d 15h /8051/tags/rel_1/
15 commbinatorial loop removed simont 7988d 15h /8051/tags/rel_1/
14 added signal ea_int simont 7988d 16h /8051/tags/rel_1/
13 some bug fix simont 7989d 13h /8051/tags/rel_1/
12 des1_r in alu port list simont 7989d 13h /8051/tags/rel_1/
11 des2_r removed simont 7989d 13h /8051/tags/rel_1/
10 % replaced with ^ in uart; some minor improvements markom 7989d 19h /8051/tags/rel_1/
9 removed unused compare states markom 7991d 12h /8051/tags/rel_1/

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