URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [rtl/] - Rev 120

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Rev	Log message	Author	Age	Path
120	defines for pherypherals added	simont	7769d 03h	/8051/tags/rel_1/rtl/
119	remove signal sbuf_txd [12:11]	simont	7769d 06h	/8051/tags/rel_1/rtl/
118	change wr_sft to 2 bit wire.	simont	7769d 23h	/8051/tags/rel_1/rtl/
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7769d 23h	/8051/tags/rel_1/rtl/
116	change sfr's interface.	simont	7772d 00h	/8051/tags/rel_1/rtl/
115	change uart to meet timing.	simont	7772d 02h	/8051/tags/rel_1/rtl/
114	remove t2mod register	simont	7775d 05h	/8051/tags/rel_1/rtl/
113	signal prsc_ow added.	simont	7775d 05h	/8051/tags/rel_1/rtl/
112	change timers to meet timing specifications (add divider with 12)	simont	7775d 05h	/8051/tags/rel_1/rtl/
110	change adr_i and adr_o length.	simont	7775d 20h	/8051/tags/rel_1/rtl/
109	add `include "oc8051_defines.v"	simont	7775d 20h	/8051/tags/rel_1/rtl/
108	fix some bugs, use oc8051_cache_ram.	simont	7775d 20h	/8051/tags/rel_1/rtl/
107	Include instruction cache.	simont	7775d 20h	/8051/tags/rel_1/rtl/
105	generic_dpram used	simont	7776d 23h	/8051/tags/rel_1/rtl/
104	use generic_dpram	simont	7776d 23h	/8051/tags/rel_1/rtl/
102	raname signals.	simont	7777d 00h	/8051/tags/rel_1/rtl/
95	updating...	simont	7777d 04h	/8051/tags/rel_1/rtl/
94	fix bug.	simont	7777d 04h	/8051/tags/rel_1/rtl/
93	OC8051_XILINX_RAM added	simont	7777d 04h	/8051/tags/rel_1/rtl/
92	initial inport	simont	7777d 04h	/8051/tags/rel_1/rtl/
90	change module name.	simont	7781d 22h	/8051/tags/rel_1/rtl/
89	Replaced oc8051_ram by generic_dpram.	rherveille	7843d 01h	/8051/tags/rel_1/rtl/
88	fix bugs	simont	7848d 01h	/8051/tags/rel_1/rtl/
87	add include oc8051_defines.v	simont	7848d 01h	/8051/tags/rel_1/rtl/
82	replace some modules	simont	7856d 01h	/8051/tags/rel_1/rtl/
81	initial import	simont	7856d 01h	/8051/tags/rel_1/rtl/
80	removing unused modules	simont	7856d 01h	/8051/tags/rel_1/rtl/
78	alu with registered outputs	simont	7916d 01h	/8051/tags/rel_1/rtl/
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	7924d 22h	/8051/tags/rel_1/rtl/
76	add module oc8051_sfr, 256 bytes internal ram	simont	7924d 22h	/8051/tags/rel_1/rtl/

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Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [rtl/] - Rev 120

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