OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

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[/] [8051/] [tags/] [rel_12/] - Rev 186

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Rev Log message Author Age Path
186 root 5510d 07h /8051/tags/rel_12/
185 root 5566d 08h /8051/tags/rel_12/
182 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7645d 01h /8051/tags/rel_12/
181 Simulation reports added. simont 7645d 01h /8051/tags/rel_12/
179 add /* synopsys xx_case */ to case statments. simont 7645d 02h /8051/tags/rel_12/
178 x replaced with 0. simont 7645d 03h /8051/tags/rel_12/
177 Fix bug in case of writing and reading from same address. simont 7656d 07h /8051/tags/rel_12/
176 ram modules added. simont 7656d 09h /8051/tags/rel_12/
175 initial inport. simont 7656d 09h /8051/tags/rel_12/
174 ram modules added. simont 7656d 09h /8051/tags/rel_12/
173 simualtion `ifdef added simont 7656d 09h /8051/tags/rel_12/
172 BIST signals added. simont 7659d 08h /8051/tags/rel_12/
171 fix bug in DA operation. simont 7667d 05h /8051/tags/rel_12/
170 removing unused files. simont 7667d 06h /8051/tags/rel_12/
169 remove unused files. simont 7667d 06h /8051/tags/rel_12/
168 modify program list. simont 7667d 06h /8051/tags/rel_12/
167 add readmem for ea. simont 7670d 12h /8051/tags/rel_12/
166 Change test monitor from ports to external data memory. simont 7671d 05h /8051/tags/rel_12/
165 remove dumpvars. simont 7671d 09h /8051/tags/rel_12/
164 initial inport. simont 7671d 10h /8051/tags/rel_12/
163 initial inport simont 7671d 10h /8051/tags/rel_12/
162 initial inport. simont 7671d 11h /8051/tags/rel_12/
161 fix file names. simont 7671d 11h /8051/tags/rel_12/
160 initial inport. simont 7671d 11h /8051/tags/rel_12/
159 initial inport. simont 7671d 11h /8051/tags/rel_12/
158 fix bug. simont 7671d 11h /8051/tags/rel_12/
157 change data output. simont 7671d 11h /8051/tags/rel_12/
156 add FREQ paremeter. simont 7671d 11h /8051/tags/rel_12/
155 add aditional tests. simont 7671d 11h /8051/tags/rel_12/
154 File name fixed. simont 7672d 06h /8051/tags/rel_12/

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