URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] - Rev 177

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Rev	Log message	Author	Age	Path
177	Fix bug in case of writing and reading from same address.	simont	7677d 22h	/8051/tags/rel_12/rtl/
175	initial inport.	simont	7678d 00h	/8051/tags/rel_12/rtl/
174	ram modules added.	simont	7678d 00h	/8051/tags/rel_12/rtl/
173	simualtion `ifdef added	simont	7678d 00h	/8051/tags/rel_12/rtl/
172	BIST signals added.	simont	7680d 23h	/8051/tags/rel_12/rtl/
171	fix bug in DA operation.	simont	7688d 21h	/8051/tags/rel_12/rtl/
158	fix bug.	simont	7693d 02h	/8051/tags/rel_12/rtl/
153	`ifdef added.	simont	7694d 20h	/8051/tags/rel_12/rtl/
152	sub_result output added.	simont	7694d 20h	/8051/tags/rel_12/rtl/
151	remove pc_r register.	simont	7694d 20h	/8051/tags/rel_12/rtl/
150	fix some bugs.	simont	7694d 20h	/8051/tags/rel_12/rtl/
149	pipelined acces to axternal instruction interface added.	simont	7694d 20h	/8051/tags/rel_12/rtl/
148	include "8051_defines" added.	simont	7694d 21h	/8051/tags/rel_12/rtl/
146	fix bug in movc intruction.	simont	7716d 21h	/8051/tags/rel_12/rtl/
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7722d 01h	/8051/tags/rel_12/rtl/
144	chsnge comp.des to des1	simont	7722d 01h	/8051/tags/rel_12/rtl/
143	add wire sub_result, conect it to des_acc and des1.	simont	7722d 01h	/8051/tags/rel_12/rtl/
142	optimize state machine.	simont	7723d 02h	/8051/tags/rel_12/rtl/
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7723d 04h	/8051/tags/rel_12/rtl/
140	cahnge assigment to pc_wait (remove istb_o)	simont	7723d 04h	/8051/tags/rel_12/rtl/
139	add aditional alu destination to solve critical path.	simont	7723d 22h	/8051/tags/rel_12/rtl/
138	Change buffering to save one clock per instruction.	simont	7723d 22h	/8051/tags/rel_12/rtl/
137	change to fit xrom.	simont	7724d 03h	/8051/tags/rel_12/rtl/
136	registering outputs.	simont	7724d 03h	/8051/tags/rel_12/rtl/
135	prepared start of receiving if ren is not active.	simont	7730d 02h	/8051/tags/rel_12/rtl/
134	fix bug in case execution of two data dependent instructions.	simont	7730d 02h	/8051/tags/rel_12/rtl/
133	fix bug in substraction.	simont	7730d 05h	/8051/tags/rel_12/rtl/
132	change branch instruction execution (reduse needed clock periods).	simont	7733d 20h	/8051/tags/rel_12/rtl/
128	chance idat_ir to 24 bit wide	simont	7743d 04h	/8051/tags/rel_12/rtl/
127	fix bug (cyc_o and stb_o)	simont	7743d 04h	/8051/tags/rel_12/rtl/

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[/] [8051/] [tags/] [rel_12/] [rtl/] - Rev 177

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