OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 175

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
175 initial inport. simont 7720d 10h /8051/tags/rel_12/rtl/verilog/
174 ram modules added. simont 7720d 10h /8051/tags/rel_12/rtl/verilog/
173 simualtion `ifdef added simont 7720d 10h /8051/tags/rel_12/rtl/verilog/
172 BIST signals added. simont 7723d 09h /8051/tags/rel_12/rtl/verilog/
171 fix bug in DA operation. simont 7731d 07h /8051/tags/rel_12/rtl/verilog/
158 fix bug. simont 7735d 12h /8051/tags/rel_12/rtl/verilog/
153 `ifdef added. simont 7737d 06h /8051/tags/rel_12/rtl/verilog/
152 sub_result output added. simont 7737d 06h /8051/tags/rel_12/rtl/verilog/
151 remove pc_r register. simont 7737d 06h /8051/tags/rel_12/rtl/verilog/
150 fix some bugs. simont 7737d 06h /8051/tags/rel_12/rtl/verilog/
149 pipelined acces to axternal instruction interface added. simont 7737d 06h /8051/tags/rel_12/rtl/verilog/
148 include "8051_defines" added. simont 7737d 07h /8051/tags/rel_12/rtl/verilog/
146 fix bug in movc intruction. simont 7759d 07h /8051/tags/rel_12/rtl/verilog/
145 fix bug in case of sequence of inc dptr instrucitons. simont 7764d 11h /8051/tags/rel_12/rtl/verilog/
144 chsnge comp.des to des1 simont 7764d 11h /8051/tags/rel_12/rtl/verilog/
143 add wire sub_result, conect it to des_acc and des1. simont 7764d 11h /8051/tags/rel_12/rtl/verilog/
142 optimize state machine. simont 7765d 12h /8051/tags/rel_12/rtl/verilog/
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7765d 14h /8051/tags/rel_12/rtl/verilog/
140 cahnge assigment to pc_wait (remove istb_o) simont 7765d 14h /8051/tags/rel_12/rtl/verilog/
139 add aditional alu destination to solve critical path. simont 7766d 08h /8051/tags/rel_12/rtl/verilog/
138 Change buffering to save one clock per instruction. simont 7766d 08h /8051/tags/rel_12/rtl/verilog/
137 change to fit xrom. simont 7766d 13h /8051/tags/rel_12/rtl/verilog/
136 registering outputs. simont 7766d 13h /8051/tags/rel_12/rtl/verilog/
135 prepared start of receiving if ren is not active. simont 7772d 12h /8051/tags/rel_12/rtl/verilog/
134 fix bug in case execution of two data dependent instructions. simont 7772d 12h /8051/tags/rel_12/rtl/verilog/
133 fix bug in substraction. simont 7772d 15h /8051/tags/rel_12/rtl/verilog/
132 change branch instruction execution (reduse needed clock periods). simont 7776d 06h /8051/tags/rel_12/rtl/verilog/
128 chance idat_ir to 24 bit wide simont 7785d 13h /8051/tags/rel_12/rtl/verilog/
127 fix bug (cyc_o and stb_o) simont 7785d 13h /8051/tags/rel_12/rtl/verilog/
126 define OC8051_XILINX_RAMB added simont 7785d 13h /8051/tags/rel_12/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.