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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 177

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Rev Log message Author Age Path
177 Fix bug in case of writing and reading from same address. simont 7727d 19h /8051/tags/rel_12/rtl/verilog/
175 initial inport. simont 7727d 21h /8051/tags/rel_12/rtl/verilog/
174 ram modules added. simont 7727d 21h /8051/tags/rel_12/rtl/verilog/
173 simualtion `ifdef added simont 7727d 21h /8051/tags/rel_12/rtl/verilog/
172 BIST signals added. simont 7730d 20h /8051/tags/rel_12/rtl/verilog/
171 fix bug in DA operation. simont 7738d 18h /8051/tags/rel_12/rtl/verilog/
158 fix bug. simont 7742d 23h /8051/tags/rel_12/rtl/verilog/
153 `ifdef added. simont 7744d 17h /8051/tags/rel_12/rtl/verilog/
152 sub_result output added. simont 7744d 17h /8051/tags/rel_12/rtl/verilog/
151 remove pc_r register. simont 7744d 17h /8051/tags/rel_12/rtl/verilog/
150 fix some bugs. simont 7744d 18h /8051/tags/rel_12/rtl/verilog/
149 pipelined acces to axternal instruction interface added. simont 7744d 18h /8051/tags/rel_12/rtl/verilog/
148 include "8051_defines" added. simont 7744d 18h /8051/tags/rel_12/rtl/verilog/
146 fix bug in movc intruction. simont 7766d 18h /8051/tags/rel_12/rtl/verilog/
145 fix bug in case of sequence of inc dptr instrucitons. simont 7771d 22h /8051/tags/rel_12/rtl/verilog/
144 chsnge comp.des to des1 simont 7771d 22h /8051/tags/rel_12/rtl/verilog/
143 add wire sub_result, conect it to des_acc and des1. simont 7771d 22h /8051/tags/rel_12/rtl/verilog/
142 optimize state machine. simont 7773d 00h /8051/tags/rel_12/rtl/verilog/
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7773d 01h /8051/tags/rel_12/rtl/verilog/
140 cahnge assigment to pc_wait (remove istb_o) simont 7773d 01h /8051/tags/rel_12/rtl/verilog/
139 add aditional alu destination to solve critical path. simont 7773d 19h /8051/tags/rel_12/rtl/verilog/
138 Change buffering to save one clock per instruction. simont 7773d 19h /8051/tags/rel_12/rtl/verilog/
137 change to fit xrom. simont 7774d 00h /8051/tags/rel_12/rtl/verilog/
136 registering outputs. simont 7774d 00h /8051/tags/rel_12/rtl/verilog/
135 prepared start of receiving if ren is not active. simont 7779d 23h /8051/tags/rel_12/rtl/verilog/
134 fix bug in case execution of two data dependent instructions. simont 7779d 23h /8051/tags/rel_12/rtl/verilog/
133 fix bug in substraction. simont 7780d 02h /8051/tags/rel_12/rtl/verilog/
132 change branch instruction execution (reduse needed clock periods). simont 7783d 17h /8051/tags/rel_12/rtl/verilog/
128 chance idat_ir to 24 bit wide simont 7793d 01h /8051/tags/rel_12/rtl/verilog/
127 fix bug (cyc_o and stb_o) simont 7793d 01h /8051/tags/rel_12/rtl/verilog/

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