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[/] [8051/] [tags/] [rel_12/] [sim/] - Rev 162

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Rev Log message Author Age Path
162 initial inport. simont 7735d 12h /8051/tags/rel_12/sim/
161 fix file names. simont 7735d 12h /8051/tags/rel_12/sim/
159 initial inport. simont 7735d 12h /8051/tags/rel_12/sim/
154 File name fixed. simont 7736d 07h /8051/tags/rel_12/sim/
106 generic_dpram used simont 7799d 07h /8051/tags/rel_12/sim/
101 initial inport simont 7799d 11h /8051/tags/rel_12/sim/
100 use \ simont 7799d 11h /8051/tags/rel_12/sim/
99 change directory structure simont 7799d 12h /8051/tags/rel_12/sim/
98 move to rtl/verilog simont 7799d 12h /8051/tags/rel_12/sim/
85 prepare bugs simont 7870d 10h /8051/tags/rel_12/sim/
83 replace some modules simont 7878d 09h /8051/tags/rel_12/sim/
82 replace some modules simont 7878d 09h /8051/tags/rel_12/sim/
69 add parameters simont 7959d 10h /8051/tags/rel_12/sim/
66 added xrom_test simont 7960d 06h /8051/tags/rel_12/sim/
65 add oc8051_icache and oc8051_cache_ram simont 7960d 06h /8051/tags/rel_12/sim/
64 signal es_int=1'b0 simont 7960d 06h /8051/tags/rel_12/sim/
63 initial import simont 7960d 06h /8051/tags/rel_12/sim/
58 add external rom testing simont 7966d 04h /8051/tags/rel_12/sim/
57 add module oc8051_xrom simont 7966d 04h /8051/tags/rel_12/sim/
56 initial CVS input simont 7966d 04h /8051/tags/rel_12/sim/
55 added parameter DELAY simont 7966d 04h /8051/tags/rel_12/sim/
46 prepared header simont 7983d 06h /8051/tags/rel_12/sim/
43 remove unused files simont 7983d 08h /8051/tags/rel_12/sim/
42 *** empty log message *** simont 7983d 08h /8051/tags/rel_12/sim/
41 remove unused files simont 7983d 08h /8051/tags/rel_12/sim/
37 added signals ack, stb and cyc simont 8010d 08h /8051/tags/rel_12/sim/
19 combinatorial loop removed simont 8024d 04h /8051/tags/rel_12/sim/
18 rst signal added simont 8027d 09h /8051/tags/rel_12/sim/
4 Code repaired to satisfy the linter; testbech fails markom 8030d 12h /8051/tags/rel_12/sim/
2 Initial CVS import simont 8046d 10h /8051/tags/rel_12/sim/

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