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[/] [8051/] [tags/] [rel_19/] - Rev 120

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Rev Log message Author Age Path
120 defines for pherypherals added simont 7789d 16h /8051/tags/rel_19/
119 remove signal sbuf_txd [12:11] simont 7789d 19h /8051/tags/rel_19/
118 change wr_sft to 2 bit wire. simont 7790d 12h /8051/tags/rel_19/
117 Register oc8051_sfr dato output, add signal wait_data. simont 7790d 13h /8051/tags/rel_19/
116 change sfr's interface. simont 7792d 13h /8051/tags/rel_19/
115 change uart to meet timing. simont 7792d 15h /8051/tags/rel_19/
114 remove t2mod register simont 7795d 18h /8051/tags/rel_19/
113 signal prsc_ow added. simont 7795d 18h /8051/tags/rel_19/
112 change timers to meet timing specifications (add divider with 12) simont 7795d 18h /8051/tags/rel_19/
111 Remove instruction cache and wb_interface simont 7796d 09h /8051/tags/rel_19/
110 change adr_i and adr_o length. simont 7796d 09h /8051/tags/rel_19/
109 add `include "oc8051_defines.v" simont 7796d 09h /8051/tags/rel_19/
108 fix some bugs, use oc8051_cache_ram. simont 7796d 09h /8051/tags/rel_19/
107 Include instruction cache. simont 7796d 09h /8051/tags/rel_19/
106 generic_dpram used simont 7797d 12h /8051/tags/rel_19/
105 generic_dpram used simont 7797d 12h /8051/tags/rel_19/
104 use generic_dpram simont 7797d 12h /8051/tags/rel_19/
103 rename signals simont 7797d 13h /8051/tags/rel_19/
102 raname signals. simont 7797d 13h /8051/tags/rel_19/
101 initial inport simont 7797d 16h /8051/tags/rel_19/
100 use \ simont 7797d 17h /8051/tags/rel_19/
99 change directory structure simont 7797d 17h /8051/tags/rel_19/
98 move to rtl/verilog simont 7797d 17h /8051/tags/rel_19/
97 initial inport simont 7797d 17h /8051/tags/rel_19/
96 initial import simont 7797d 17h /8051/tags/rel_19/
95 updating... simont 7797d 17h /8051/tags/rel_19/
94 fix bug. simont 7797d 17h /8051/tags/rel_19/
93 OC8051_XILINX_RAM added simont 7797d 17h /8051/tags/rel_19/
92 initial inport simont 7797d 17h /8051/tags/rel_19/
91 *** empty log message *** simont 7797d 17h /8051/tags/rel_19/

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