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[/] [8051/] [tags/] [rel_19/] [bench/] - Rev 186

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Rev Log message Author Age Path
186 root 5530d 14h /8051/tags/rel_19/bench/
185 root 5586d 15h /8051/tags/rel_19/bench/
183 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7665d 07h /8051/tags/rel_19/bench/
170 removing unused files. simont 7687d 13h /8051/tags/rel_19/bench/
169 remove unused files. simont 7687d 13h /8051/tags/rel_19/bench/
167 add readmem for ea. simont 7690d 19h /8051/tags/rel_19/bench/
166 Change test monitor from ports to external data memory. simont 7691d 12h /8051/tags/rel_19/bench/
165 remove dumpvars. simont 7691d 16h /8051/tags/rel_19/bench/
164 initial inport. simont 7691d 17h /8051/tags/rel_19/bench/
163 initial inport simont 7691d 17h /8051/tags/rel_19/bench/
157 change data output. simont 7691d 18h /8051/tags/rel_19/bench/
156 add FREQ paremeter. simont 7691d 18h /8051/tags/rel_19/bench/
155 add aditional tests. simont 7691d 18h /8051/tags/rel_19/bench/
130 prepared programs for new timing. simont 7732d 12h /8051/tags/rel_19/bench/
129 updated... simont 7732d 12h /8051/tags/rel_19/bench/
125 update, add prescaler, rclk, tclk. simont 7741d 19h /8051/tags/rel_19/bench/
124 add support for external rom from xilinx ramb4 simont 7741d 19h /8051/tags/rel_19/bench/
120 defines for pherypherals added simont 7747d 16h /8051/tags/rel_19/bench/
111 Remove instruction cache and wb_interface simont 7754d 10h /8051/tags/rel_19/bench/
103 rename signals simont 7755d 14h /8051/tags/rel_19/bench/
97 initial inport simont 7755d 18h /8051/tags/rel_19/bench/
96 initial import simont 7755d 18h /8051/tags/rel_19/bench/
84 remove wb_bus_mon simont 7834d 15h /8051/tags/rel_19/bench/
74 add module oc8051_wb_iinterface simont 7911d 12h /8051/tags/rel_19/bench/
68 add instruction cache and DELAY parameters for external ram, rom simont 7915d 16h /8051/tags/rel_19/bench/
59 add external rom simont 7922d 10h /8051/tags/rel_19/bench/
46 prepared header simont 7939d 12h /8051/tags/rel_19/bench/
37 added signals ack, stb and cyc simont 7966d 14h /8051/tags/rel_19/bench/
4 Code repaired to satisfy the linter; testbech fails markom 7986d 18h /8051/tags/rel_19/bench/
2 Initial CVS import simont 8002d 16h /8051/tags/rel_19/bench/

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