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[/] [8051/] [tags/] [rel_2/] - Rev 120

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Rev	Log message	Author	Age	Path
120	defines for pherypherals added	simont	7784d 21h	/8051/tags/rel_2/
119	remove signal sbuf_txd [12:11]	simont	7785d 01h	/8051/tags/rel_2/
118	change wr_sft to 2 bit wire.	simont	7785d 17h	/8051/tags/rel_2/
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7785d 18h	/8051/tags/rel_2/
116	change sfr's interface.	simont	7787d 19h	/8051/tags/rel_2/
115	change uart to meet timing.	simont	7787d 20h	/8051/tags/rel_2/
114	remove t2mod register	simont	7790d 23h	/8051/tags/rel_2/
113	signal prsc_ow added.	simont	7790d 23h	/8051/tags/rel_2/
112	change timers to meet timing specifications (add divider with 12)	simont	7790d 23h	/8051/tags/rel_2/
111	Remove instruction cache and wb_interface	simont	7791d 14h	/8051/tags/rel_2/
110	change adr_i and adr_o length.	simont	7791d 14h	/8051/tags/rel_2/
109	add `include "oc8051_defines.v"	simont	7791d 14h	/8051/tags/rel_2/
108	fix some bugs, use oc8051_cache_ram.	simont	7791d 14h	/8051/tags/rel_2/
107	Include instruction cache.	simont	7791d 14h	/8051/tags/rel_2/
106	generic_dpram used	simont	7792d 17h	/8051/tags/rel_2/
105	generic_dpram used	simont	7792d 17h	/8051/tags/rel_2/
104	use generic_dpram	simont	7792d 17h	/8051/tags/rel_2/
103	rename signals	simont	7792d 19h	/8051/tags/rel_2/
102	raname signals.	simont	7792d 19h	/8051/tags/rel_2/
101	initial inport	simont	7792d 22h	/8051/tags/rel_2/
100	use \	simont	7792d 22h	/8051/tags/rel_2/
99	change directory structure	simont	7792d 22h	/8051/tags/rel_2/
98	move to rtl/verilog	simont	7792d 22h	/8051/tags/rel_2/
97	initial inport	simont	7792d 22h	/8051/tags/rel_2/
96	initial import	simont	7792d 22h	/8051/tags/rel_2/
95	updating...	simont	7792d 22h	/8051/tags/rel_2/
94	fix bug.	simont	7792d 22h	/8051/tags/rel_2/
93	OC8051_XILINX_RAM added	simont	7792d 22h	/8051/tags/rel_2/
92	initial inport	simont	7792d 22h	/8051/tags/rel_2/
91	* empty log message *	simont	7792d 22h	/8051/tags/rel_2/

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Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] - Rev 120

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