URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [bench/] - Rev 164

Rev	Log message	Author	Age	Path
164	initial inport.	simont	7727d 00h	/8051/tags/rel_2/bench/
163	initial inport	simont	7727d 00h	/8051/tags/rel_2/bench/
157	change data output.	simont	7727d 01h	/8051/tags/rel_2/bench/
156	add FREQ paremeter.	simont	7727d 01h	/8051/tags/rel_2/bench/
155	add aditional tests.	simont	7727d 01h	/8051/tags/rel_2/bench/
130	prepared programs for new timing.	simont	7767d 19h	/8051/tags/rel_2/bench/
129	updated...	simont	7767d 19h	/8051/tags/rel_2/bench/
125	update, add prescaler, rclk, tclk.	simont	7777d 03h	/8051/tags/rel_2/bench/
124	add support for external rom from xilinx ramb4	simont	7777d 03h	/8051/tags/rel_2/bench/
120	defines for pherypherals added	simont	7783d 00h	/8051/tags/rel_2/bench/
111	Remove instruction cache and wb_interface	simont	7789d 17h	/8051/tags/rel_2/bench/
103	rename signals	simont	7790d 21h	/8051/tags/rel_2/bench/
97	initial inport	simont	7791d 01h	/8051/tags/rel_2/bench/
96	initial import	simont	7791d 01h	/8051/tags/rel_2/bench/
84	remove wb_bus_mon	simont	7869d 22h	/8051/tags/rel_2/bench/
74	add module oc8051_wb_iinterface	simont	7946d 20h	/8051/tags/rel_2/bench/
68	add instruction cache and DELAY parameters for external ram, rom	simont	7950d 23h	/8051/tags/rel_2/bench/
59	add external rom	simont	7957d 18h	/8051/tags/rel_2/bench/
46	prepared header	simont	7974d 19h	/8051/tags/rel_2/bench/
37	added signals ack, stb and cyc	simont	8001d 21h	/8051/tags/rel_2/bench/
4	Code repaired to satisfy the linter; testbech fails	markom	8022d 01h	/8051/tags/rel_2/bench/
2	Initial CVS import	simont	8037d 23h	/8051/tags/rel_2/bench/