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[/] [8051/] [tags/] [rel_2/] [rtl/] - Rev 150

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Rev Log message Author Age Path
150 fix some bugs. simont 7728d 19h /8051/tags/rel_2/rtl/
149 pipelined acces to axternal instruction interface added. simont 7728d 19h /8051/tags/rel_2/rtl/
148 include "8051_defines" added. simont 7728d 19h /8051/tags/rel_2/rtl/
146 fix bug in movc intruction. simont 7750d 20h /8051/tags/rel_2/rtl/
145 fix bug in case of sequence of inc dptr instrucitons. simont 7756d 00h /8051/tags/rel_2/rtl/
144 chsnge comp.des to des1 simont 7756d 00h /8051/tags/rel_2/rtl/
143 add wire sub_result, conect it to des_acc and des1. simont 7756d 00h /8051/tags/rel_2/rtl/
142 optimize state machine. simont 7757d 01h /8051/tags/rel_2/rtl/
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7757d 03h /8051/tags/rel_2/rtl/
140 cahnge assigment to pc_wait (remove istb_o) simont 7757d 03h /8051/tags/rel_2/rtl/
139 add aditional alu destination to solve critical path. simont 7757d 20h /8051/tags/rel_2/rtl/
138 Change buffering to save one clock per instruction. simont 7757d 21h /8051/tags/rel_2/rtl/
137 change to fit xrom. simont 7758d 02h /8051/tags/rel_2/rtl/
136 registering outputs. simont 7758d 02h /8051/tags/rel_2/rtl/
135 prepared start of receiving if ren is not active. simont 7764d 01h /8051/tags/rel_2/rtl/
134 fix bug in case execution of two data dependent instructions. simont 7764d 01h /8051/tags/rel_2/rtl/
133 fix bug in substraction. simont 7764d 04h /8051/tags/rel_2/rtl/
132 change branch instruction execution (reduse needed clock periods). simont 7767d 19h /8051/tags/rel_2/rtl/
128 chance idat_ir to 24 bit wide simont 7777d 02h /8051/tags/rel_2/rtl/
127 fix bug (cyc_o and stb_o) simont 7777d 02h /8051/tags/rel_2/rtl/
126 define OC8051_XILINX_RAMB added simont 7777d 02h /8051/tags/rel_2/rtl/
123 fiz bug iv pcs operation. simont 7778d 22h /8051/tags/rel_2/rtl/
122 deifne OC8051_ROM added simont 7782d 02h /8051/tags/rel_2/rtl/
121 Change pc add value from 23'h to 16'h simont 7782d 02h /8051/tags/rel_2/rtl/
120 defines for pherypherals added simont 7783d 00h /8051/tags/rel_2/rtl/
119 remove signal sbuf_txd [12:11] simont 7783d 03h /8051/tags/rel_2/rtl/
118 change wr_sft to 2 bit wire. simont 7783d 20h /8051/tags/rel_2/rtl/
117 Register oc8051_sfr dato output, add signal wait_data. simont 7783d 20h /8051/tags/rel_2/rtl/
116 change sfr's interface. simont 7785d 21h /8051/tags/rel_2/rtl/
115 change uart to meet timing. simont 7785d 23h /8051/tags/rel_2/rtl/

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