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[/] [8051/] [tags/] [rel_2/] [rtl/] - Rev 178

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Rev Log message Author Age Path
178 x replaced with 0. simont 7676d 11h /8051/tags/rel_2/rtl/
177 Fix bug in case of writing and reading from same address. simont 7687d 14h /8051/tags/rel_2/rtl/
175 initial inport. simont 7687d 16h /8051/tags/rel_2/rtl/
174 ram modules added. simont 7687d 16h /8051/tags/rel_2/rtl/
173 simualtion `ifdef added simont 7687d 16h /8051/tags/rel_2/rtl/
172 BIST signals added. simont 7690d 15h /8051/tags/rel_2/rtl/
171 fix bug in DA operation. simont 7698d 13h /8051/tags/rel_2/rtl/
158 fix bug. simont 7702d 18h /8051/tags/rel_2/rtl/
153 `ifdef added. simont 7704d 12h /8051/tags/rel_2/rtl/
152 sub_result output added. simont 7704d 12h /8051/tags/rel_2/rtl/
151 remove pc_r register. simont 7704d 12h /8051/tags/rel_2/rtl/
150 fix some bugs. simont 7704d 12h /8051/tags/rel_2/rtl/
149 pipelined acces to axternal instruction interface added. simont 7704d 12h /8051/tags/rel_2/rtl/
148 include "8051_defines" added. simont 7704d 13h /8051/tags/rel_2/rtl/
146 fix bug in movc intruction. simont 7726d 13h /8051/tags/rel_2/rtl/
145 fix bug in case of sequence of inc dptr instrucitons. simont 7731d 17h /8051/tags/rel_2/rtl/
144 chsnge comp.des to des1 simont 7731d 17h /8051/tags/rel_2/rtl/
143 add wire sub_result, conect it to des_acc and des1. simont 7731d 17h /8051/tags/rel_2/rtl/
142 optimize state machine. simont 7732d 18h /8051/tags/rel_2/rtl/
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7732d 20h /8051/tags/rel_2/rtl/
140 cahnge assigment to pc_wait (remove istb_o) simont 7732d 20h /8051/tags/rel_2/rtl/
139 add aditional alu destination to solve critical path. simont 7733d 14h /8051/tags/rel_2/rtl/
138 Change buffering to save one clock per instruction. simont 7733d 14h /8051/tags/rel_2/rtl/
137 change to fit xrom. simont 7733d 19h /8051/tags/rel_2/rtl/
136 registering outputs. simont 7733d 19h /8051/tags/rel_2/rtl/
135 prepared start of receiving if ren is not active. simont 7739d 18h /8051/tags/rel_2/rtl/
134 fix bug in case execution of two data dependent instructions. simont 7739d 18h /8051/tags/rel_2/rtl/
133 fix bug in substraction. simont 7739d 21h /8051/tags/rel_2/rtl/
132 change branch instruction execution (reduse needed clock periods). simont 7743d 12h /8051/tags/rel_2/rtl/
128 chance idat_ir to 24 bit wide simont 7752d 20h /8051/tags/rel_2/rtl/

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