OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [rtl/] - Rev 186

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
186 root 5520d 14h /8051/tags/rel_2/rtl/
185 root 5576d 15h /8051/tags/rel_2/rtl/
180 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7655d 08h /8051/tags/rel_2/rtl/
179 add /* synopsys xx_case */ to case statments. simont 7655d 08h /8051/tags/rel_2/rtl/
178 x replaced with 0. simont 7655d 10h /8051/tags/rel_2/rtl/
177 Fix bug in case of writing and reading from same address. simont 7666d 13h /8051/tags/rel_2/rtl/
175 initial inport. simont 7666d 15h /8051/tags/rel_2/rtl/
174 ram modules added. simont 7666d 15h /8051/tags/rel_2/rtl/
173 simualtion `ifdef added simont 7666d 15h /8051/tags/rel_2/rtl/
172 BIST signals added. simont 7669d 15h /8051/tags/rel_2/rtl/
171 fix bug in DA operation. simont 7677d 12h /8051/tags/rel_2/rtl/
158 fix bug. simont 7681d 18h /8051/tags/rel_2/rtl/
153 `ifdef added. simont 7683d 12h /8051/tags/rel_2/rtl/
152 sub_result output added. simont 7683d 12h /8051/tags/rel_2/rtl/
151 remove pc_r register. simont 7683d 12h /8051/tags/rel_2/rtl/
150 fix some bugs. simont 7683d 12h /8051/tags/rel_2/rtl/
149 pipelined acces to axternal instruction interface added. simont 7683d 12h /8051/tags/rel_2/rtl/
148 include "8051_defines" added. simont 7683d 12h /8051/tags/rel_2/rtl/
146 fix bug in movc intruction. simont 7705d 12h /8051/tags/rel_2/rtl/
145 fix bug in case of sequence of inc dptr instrucitons. simont 7710d 16h /8051/tags/rel_2/rtl/
144 chsnge comp.des to des1 simont 7710d 16h /8051/tags/rel_2/rtl/
143 add wire sub_result, conect it to des_acc and des1. simont 7710d 16h /8051/tags/rel_2/rtl/
142 optimize state machine. simont 7711d 18h /8051/tags/rel_2/rtl/
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7711d 19h /8051/tags/rel_2/rtl/
140 cahnge assigment to pc_wait (remove istb_o) simont 7711d 19h /8051/tags/rel_2/rtl/
139 add aditional alu destination to solve critical path. simont 7712d 13h /8051/tags/rel_2/rtl/
138 Change buffering to save one clock per instruction. simont 7712d 13h /8051/tags/rel_2/rtl/
137 change to fit xrom. simont 7712d 18h /8051/tags/rel_2/rtl/
136 registering outputs. simont 7712d 18h /8051/tags/rel_2/rtl/
135 prepared start of receiving if ren is not active. simont 7718d 17h /8051/tags/rel_2/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.