URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [sim/] - Rev 154

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Rev	Log message	Author	Age	Path
154	File name fixed.	simont	7734d 15h	/8051/tags/rel_2/sim/
106	generic_dpram used	simont	7797d 15h	/8051/tags/rel_2/sim/
101	initial inport	simont	7797d 19h	/8051/tags/rel_2/sim/
100	use \	simont	7797d 19h	/8051/tags/rel_2/sim/
99	change directory structure	simont	7797d 19h	/8051/tags/rel_2/sim/
98	move to rtl/verilog	simont	7797d 19h	/8051/tags/rel_2/sim/
85	prepare bugs	simont	7868d 18h	/8051/tags/rel_2/sim/
83	replace some modules	simont	7876d 17h	/8051/tags/rel_2/sim/
82	replace some modules	simont	7876d 17h	/8051/tags/rel_2/sim/
69	add parameters	simont	7957d 18h	/8051/tags/rel_2/sim/
66	added xrom_test	simont	7958d 14h	/8051/tags/rel_2/sim/
65	add oc8051_icache and oc8051_cache_ram	simont	7958d 14h	/8051/tags/rel_2/sim/
64	signal es_int=1'b0	simont	7958d 14h	/8051/tags/rel_2/sim/
63	initial import	simont	7958d 14h	/8051/tags/rel_2/sim/
58	add external rom testing	simont	7964d 12h	/8051/tags/rel_2/sim/
57	add module oc8051_xrom	simont	7964d 12h	/8051/tags/rel_2/sim/
56	initial CVS input	simont	7964d 12h	/8051/tags/rel_2/sim/
55	added parameter DELAY	simont	7964d 12h	/8051/tags/rel_2/sim/
46	prepared header	simont	7981d 14h	/8051/tags/rel_2/sim/
43	remove unused files	simont	7981d 15h	/8051/tags/rel_2/sim/
42	* empty log message *	simont	7981d 16h	/8051/tags/rel_2/sim/
41	remove unused files	simont	7981d 16h	/8051/tags/rel_2/sim/
37	added signals ack, stb and cyc	simont	8008d 16h	/8051/tags/rel_2/sim/
19	combinatorial loop removed	simont	8022d 12h	/8051/tags/rel_2/sim/
18	rst signal added	simont	8025d 17h	/8051/tags/rel_2/sim/
4	Code repaired to satisfy the linter; testbech fails	markom	8028d 20h	/8051/tags/rel_2/sim/
2	Initial CVS import	simont	8044d 18h	/8051/tags/rel_2/sim/

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Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [sim/] - Rev 154

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