OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [sim/] - Rev 186

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
186 root 5521d 10h /8051/tags/rel_2/sim/
185 root 5577d 12h /8051/tags/rel_2/sim/
180 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7656d 05h /8051/tags/rel_2/sim/
176 ram modules added. simont 7667d 12h /8051/tags/rel_2/sim/
168 modify program list. simont 7678d 10h /8051/tags/rel_2/sim/
162 initial inport. simont 7682d 14h /8051/tags/rel_2/sim/
161 fix file names. simont 7682d 14h /8051/tags/rel_2/sim/
159 initial inport. simont 7682d 14h /8051/tags/rel_2/sim/
154 File name fixed. simont 7683d 09h /8051/tags/rel_2/sim/
106 generic_dpram used simont 7746d 09h /8051/tags/rel_2/sim/
101 initial inport simont 7746d 14h /8051/tags/rel_2/sim/
100 use \ simont 7746d 14h /8051/tags/rel_2/sim/
99 change directory structure simont 7746d 14h /8051/tags/rel_2/sim/
98 move to rtl/verilog simont 7746d 14h /8051/tags/rel_2/sim/
85 prepare bugs simont 7817d 12h /8051/tags/rel_2/sim/
83 replace some modules simont 7825d 11h /8051/tags/rel_2/sim/
82 replace some modules simont 7825d 11h /8051/tags/rel_2/sim/
69 add parameters simont 7906d 12h /8051/tags/rel_2/sim/
66 added xrom_test simont 7907d 09h /8051/tags/rel_2/sim/
65 add oc8051_icache and oc8051_cache_ram simont 7907d 09h /8051/tags/rel_2/sim/
64 signal es_int=1'b0 simont 7907d 09h /8051/tags/rel_2/sim/
63 initial import simont 7907d 09h /8051/tags/rel_2/sim/
58 add external rom testing simont 7913d 07h /8051/tags/rel_2/sim/
57 add module oc8051_xrom simont 7913d 07h /8051/tags/rel_2/sim/
56 initial CVS input simont 7913d 07h /8051/tags/rel_2/sim/
55 added parameter DELAY simont 7913d 07h /8051/tags/rel_2/sim/
46 prepared header simont 7930d 08h /8051/tags/rel_2/sim/
43 remove unused files simont 7930d 10h /8051/tags/rel_2/sim/
42 *** empty log message *** simont 7930d 10h /8051/tags/rel_2/sim/
41 remove unused files simont 7930d 10h /8051/tags/rel_2/sim/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.