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URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] - Rev 140

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Rev Log message Author Age Path
140 cahnge assigment to pc_wait (remove istb_o) simont 7735d 21h /8051/trunk/
139 add aditional alu destination to solve critical path. simont 7736d 15h /8051/trunk/
138 Change buffering to save one clock per instruction. simont 7736d 15h /8051/trunk/
137 change to fit xrom. simont 7736d 21h /8051/trunk/
136 registering outputs. simont 7736d 21h /8051/trunk/
135 prepared start of receiving if ren is not active. simont 7742d 20h /8051/trunk/
134 fix bug in case execution of two data dependent instructions. simont 7742d 20h /8051/trunk/
133 fix bug in substraction. simont 7742d 23h /8051/trunk/
132 change branch instruction execution (reduse needed clock periods). simont 7746d 14h /8051/trunk/
131 prepare programs for new timing. simont 7746d 14h /8051/trunk/
130 prepared programs for new timing. simont 7746d 14h /8051/trunk/
129 updated... simont 7746d 14h /8051/trunk/
128 chance idat_ir to 24 bit wide simont 7755d 21h /8051/trunk/
127 fix bug (cyc_o and stb_o) simont 7755d 21h /8051/trunk/
126 define OC8051_XILINX_RAMB added simont 7755d 21h /8051/trunk/
125 update, add prescaler, rclk, tclk. simont 7755d 21h /8051/trunk/
124 add support for external rom from xilinx ramb4 simont 7755d 21h /8051/trunk/
123 fiz bug iv pcs operation. simont 7757d 17h /8051/trunk/
122 deifne OC8051_ROM added simont 7760d 21h /8051/trunk/
121 Change pc add value from 23'h to 16'h simont 7760d 21h /8051/trunk/
120 defines for pherypherals added simont 7761d 18h /8051/trunk/
119 remove signal sbuf_txd [12:11] simont 7761d 22h /8051/trunk/
118 change wr_sft to 2 bit wire. simont 7762d 15h /8051/trunk/
117 Register oc8051_sfr dato output, add signal wait_data. simont 7762d 15h /8051/trunk/
116 change sfr's interface. simont 7764d 16h /8051/trunk/
115 change uart to meet timing. simont 7764d 18h /8051/trunk/
114 remove t2mod register simont 7767d 20h /8051/trunk/
113 signal prsc_ow added. simont 7767d 21h /8051/trunk/
112 change timers to meet timing specifications (add divider with 12) simont 7767d 21h /8051/trunk/
111 Remove instruction cache and wb_interface simont 7768d 12h /8051/trunk/

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