OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] - Rev 37

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Rev Log message Author Age Path
37 added signals ack, stb and cyc simont 7987d 21h /8051/trunk/
36 fix bugs in mode 0 simont 7987d 21h /8051/trunk/
35 design docunemt simont 7988d 19h /8051/trunk/
34 specification docunemt simont 7988d 19h /8051/trunk/
33 fix some bugs simont 7989d 00h /8051/trunk/
32 overflow repaired simont 7989d 01h /8051/trunk/
31 fix some bugs simont 7995d 17h /8051/trunk/
30 mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32 simont 7999d 00h /8051/trunk/
29 fix some bugs simont 7999d 00h /8051/trunk/
28 remove syn signal simont 7999d 01h /8051/trunk/
27 fix some bugs simont 7999d 01h /8051/trunk/
26 main divider logic was optimized not optimized by compiler, so I did it by hand markom 7999d 02h /8051/trunk/
25 divider and multiplier pass test markom 7999d 21h /8051/trunk/
24 intensively tests all instructions markom 8000d 02h /8051/trunk/
23 mul & div use 4 clocks simont 8000d 16h /8051/trunk/
22 fix some bugs simont 8000d 16h /8051/trunk/
21 mul bug fixed markom 8000d 22h /8051/trunk/
20 multiplier and divider changed so they complete in 4 cycles markom 8001d 00h /8051/trunk/
19 combinatorial loop removed simont 8001d 17h /8051/trunk/
18 rst signal added simont 8004d 22h /8051/trunk/
17 fix some bugs simont 8004d 22h /8051/trunk/
16 inputs ram and op2 removed simont 8004d 22h /8051/trunk/
15 commbinatorial loop removed simont 8004d 22h /8051/trunk/
14 added signal ea_int simont 8004d 23h /8051/trunk/
13 some bug fix simont 8005d 20h /8051/trunk/
12 des1_r in alu port list simont 8005d 20h /8051/trunk/
11 des2_r removed simont 8005d 20h /8051/trunk/
10 % replaced with ^ in uart; some minor improvements markom 8006d 02h /8051/trunk/
9 removed unused compare states markom 8007d 19h /8051/trunk/
8 some IDS optimizations markom 8007d 19h /8051/trunk/

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