OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] - Rev 44

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Rev Log message Author Age Path
44 prepared header simont 8023d 21h /8051/trunk/
43 remove unused files simont 8023d 22h /8051/trunk/
42 *** empty log message *** simont 8023d 22h /8051/trunk/
41 remove unused files simont 8023d 22h /8051/trunk/
40 added sigals for interacting with external ram simont 8044d 00h /8051/trunk/
39 added signals ack, stb and cyc simont 8050d 22h /8051/trunk/
38 fix some bugs simont 8050d 22h /8051/trunk/
37 added signals ack, stb and cyc simont 8050d 22h /8051/trunk/
36 fix bugs in mode 0 simont 8050d 22h /8051/trunk/
35 design docunemt simont 8051d 21h /8051/trunk/
34 specification docunemt simont 8051d 21h /8051/trunk/
33 fix some bugs simont 8052d 02h /8051/trunk/
32 overflow repaired simont 8052d 03h /8051/trunk/
31 fix some bugs simont 8058d 19h /8051/trunk/
30 mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32 simont 8062d 01h /8051/trunk/
29 fix some bugs simont 8062d 02h /8051/trunk/
28 remove syn signal simont 8062d 02h /8051/trunk/
27 fix some bugs simont 8062d 03h /8051/trunk/
26 main divider logic was optimized not optimized by compiler, so I did it by hand markom 8062d 04h /8051/trunk/
25 divider and multiplier pass test markom 8062d 23h /8051/trunk/
24 intensively tests all instructions markom 8063d 04h /8051/trunk/
23 mul & div use 4 clocks simont 8063d 18h /8051/trunk/
22 fix some bugs simont 8063d 18h /8051/trunk/
21 mul bug fixed markom 8064d 00h /8051/trunk/
20 multiplier and divider changed so they complete in 4 cycles markom 8064d 02h /8051/trunk/
19 combinatorial loop removed simont 8064d 18h /8051/trunk/
18 rst signal added simont 8068d 00h /8051/trunk/
17 fix some bugs simont 8068d 00h /8051/trunk/
16 inputs ram and op2 removed simont 8068d 00h /8051/trunk/
15 commbinatorial loop removed simont 8068d 00h /8051/trunk/

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