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URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] - Rev 151

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Rev Log message Author Age Path
151 remove pc_r register. simont 7736d 01h /8051/trunk/rtl/verilog/
150 fix some bugs. simont 7736d 01h /8051/trunk/rtl/verilog/
149 pipelined acces to axternal instruction interface added. simont 7736d 01h /8051/trunk/rtl/verilog/
148 include "8051_defines" added. simont 7736d 02h /8051/trunk/rtl/verilog/
146 fix bug in movc intruction. simont 7758d 02h /8051/trunk/rtl/verilog/
145 fix bug in case of sequence of inc dptr instrucitons. simont 7763d 06h /8051/trunk/rtl/verilog/
144 chsnge comp.des to des1 simont 7763d 06h /8051/trunk/rtl/verilog/
143 add wire sub_result, conect it to des_acc and des1. simont 7763d 06h /8051/trunk/rtl/verilog/
142 optimize state machine. simont 7764d 07h /8051/trunk/rtl/verilog/
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7764d 09h /8051/trunk/rtl/verilog/
140 cahnge assigment to pc_wait (remove istb_o) simont 7764d 09h /8051/trunk/rtl/verilog/
139 add aditional alu destination to solve critical path. simont 7765d 03h /8051/trunk/rtl/verilog/
138 Change buffering to save one clock per instruction. simont 7765d 03h /8051/trunk/rtl/verilog/
137 change to fit xrom. simont 7765d 08h /8051/trunk/rtl/verilog/
136 registering outputs. simont 7765d 08h /8051/trunk/rtl/verilog/
135 prepared start of receiving if ren is not active. simont 7771d 07h /8051/trunk/rtl/verilog/
134 fix bug in case execution of two data dependent instructions. simont 7771d 07h /8051/trunk/rtl/verilog/
133 fix bug in substraction. simont 7771d 10h /8051/trunk/rtl/verilog/
132 change branch instruction execution (reduse needed clock periods). simont 7775d 01h /8051/trunk/rtl/verilog/
128 chance idat_ir to 24 bit wide simont 7784d 08h /8051/trunk/rtl/verilog/
127 fix bug (cyc_o and stb_o) simont 7784d 09h /8051/trunk/rtl/verilog/
126 define OC8051_XILINX_RAMB added simont 7784d 09h /8051/trunk/rtl/verilog/
123 fiz bug iv pcs operation. simont 7786d 04h /8051/trunk/rtl/verilog/
122 deifne OC8051_ROM added simont 7789d 08h /8051/trunk/rtl/verilog/
121 Change pc add value from 23'h to 16'h simont 7789d 08h /8051/trunk/rtl/verilog/
120 defines for pherypherals added simont 7790d 06h /8051/trunk/rtl/verilog/
119 remove signal sbuf_txd [12:11] simont 7790d 10h /8051/trunk/rtl/verilog/
118 change wr_sft to 2 bit wire. simont 7791d 02h /8051/trunk/rtl/verilog/
117 Register oc8051_sfr dato output, add signal wait_data. simont 7791d 03h /8051/trunk/rtl/verilog/
116 change sfr's interface. simont 7793d 04h /8051/trunk/rtl/verilog/

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