OpenCores
URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [branches/] [AEMB2_712/] - Rev 194

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
191 New directory structure. root 5585d 18h /aemb/branches/AEMB2_712/
77 This commit was manufactured by cvs2svn to create branch 'AEMB2_712'. 6043d 18h /branches/AEMB2_712/
76 initial sybreon 6043d 18h /trunk/
74 Minor code cleanup. sybreon 6050d 19h /trunk/
73 Moved simulation kernel into code. sybreon 6050d 19h /trunk/
72 Minor code cleanup. sybreon 6050d 20h /trunk/
71 Old version deprecated. sybreon 6057d 22h /trunk/
70 Change interrupt to positive level triggered interrupts. sybreon 6058d 21h /trunk/
69 Removed unnecessary byte acrobatics with VMEM data. sybreon 6060d 18h /trunk/
68 Generate VMEM instead of HEX dumps of programme. sybreon 6060d 18h /trunk/
67 Minor simulation fixes. sybreon 6062d 17h /trunk/
66 Added fsl_tag_o to FSL bus (tag either address or data). sybreon 6064d 15h /trunk/
65 Fixed minor typo causing synthesis failure. sybreon 6066d 03h /trunk/
64 Fixed minor interrupt test typo. sybreon 6066d 13h /trunk/
63 Fixed interrupt signal synchronisation. sybreon 6066d 13h /trunk/
62 Fixed minor typo. sybreon 6066d 13h /trunk/
61 Changed interrupt handling system (reported by M. Ettus). sybreon 6066d 14h /trunk/
60 Added interrupt test routine. sybreon 6066d 14h /trunk/
59 Added posedge/negedge bus interface.
Modified interrupt test system.		 sybreon 6066d 14h /trunk/
58 Updated simulation to also check BRI 0x00 instruction. sybreon 6067d 13h /trunk/
57 Updated documentation to EDK32 version. sybreon 6069d 14h /trunk/
56 Parameterised optional components into aeMB_xecu.v sybreon 6070d 12h /trunk/
55 Upgraded license to LGPLv3.
Significant performance optimisations.		 sybreon 6070d 20h /trunk/
54 Added some compilation optimisations. sybreon 6071d 16h /trunk/
53 Added GET/PUT support through a FSL bus. sybreon 6071d 16h /trunk/
52 Added log output to iverilog.log sybreon 6071d 16h /trunk/
51 Fixed data WISHBONE arbitration problem (reported by J Lee). sybreon 6072d 19h /trunk/
50 Parameterised optional components. sybreon 6072d 22h /trunk/
49 Added random seed for simulation. sybreon 6076d 01h /trunk/
48 Fixed spurious interrupt latching during long bus cycles (spotted by J Lee). sybreon 6077d 07h /trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.