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Rev Log message Author Age Path
191 New directory structure. root 5600d 22h /aemb/branches/AEMB2_712/rtl/
77 This commit was manufactured by cvs2svn to create branch 'AEMB2_712'. 6058d 22h /aemb/branches/AEMB2_712/rtl/
76 initial sybreon 6058d 22h /aemb/branches/AEMB2_712/rtl/
73 Moved simulation kernel into code. sybreon 6066d 00h /aemb/branches/AEMB2_712/rtl/
72 Minor code cleanup. sybreon 6066d 00h /aemb/branches/AEMB2_712/rtl/
71 Old version deprecated. sybreon 6073d 03h /aemb/branches/AEMB2_712/rtl/
70 Change interrupt to positive level triggered interrupts. sybreon 6074d 02h /aemb/branches/AEMB2_712/rtl/
66 Added fsl_tag_o to FSL bus (tag either address or data). sybreon 6079d 19h /aemb/branches/AEMB2_712/rtl/
65 Fixed minor typo causing synthesis failure. sybreon 6081d 07h /aemb/branches/AEMB2_712/rtl/
63 Fixed interrupt signal synchronisation. sybreon 6081d 17h /aemb/branches/AEMB2_712/rtl/
62 Fixed minor typo. sybreon 6081d 17h /aemb/branches/AEMB2_712/rtl/
61 Changed interrupt handling system (reported by M. Ettus). sybreon 6081d 18h /aemb/branches/AEMB2_712/rtl/
56 Parameterised optional components into aeMB_xecu.v sybreon 6085d 17h /aemb/branches/AEMB2_712/rtl/
55 Upgraded license to LGPLv3.
Significant performance optimisations.		 sybreon 6086d 00h /aemb/branches/AEMB2_712/rtl/
53 Added GET/PUT support through a FSL bus. sybreon 6086d 20h /aemb/branches/AEMB2_712/rtl/
51 Fixed data WISHBONE arbitration problem (reported by J Lee). sybreon 6087d 23h /aemb/branches/AEMB2_712/rtl/
50 Parameterised optional components. sybreon 6088d 02h /aemb/branches/AEMB2_712/rtl/
48 Fixed spurious interrupt latching during long bus cycles (spotted by J Lee). sybreon 6092d 11h /aemb/branches/AEMB2_712/rtl/
45 Minor code cleanup. sybreon 6093d 08h /aemb/branches/AEMB2_712/rtl/
44 Added better (beta) interrupt support.
Changed MSR_IE to disabled at reset as per MB docs.		 sybreon 6093d 21h /aemb/branches/AEMB2_712/rtl/
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6094d 13h /aemb/branches/AEMB2_712/rtl/
39 Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. sybreon 6104d 22h /aemb/branches/AEMB2_712/rtl/
38 Added interrupt support. sybreon 6249d 22h /aemb/branches/AEMB2_712/rtl/
36 Removed asynchronous reset signal. sybreon 6263d 08h /aemb/branches/AEMB2_712/rtl/
35 Added async BRA/DLY signals for future clock, reset, and interrupt features. sybreon 6264d 04h /aemb/branches/AEMB2_712/rtl/
34 Corrected speed issues after rev 1.9 update. sybreon 6264d 18h /aemb/branches/AEMB2_712/rtl/
33 Fixed minor data hazard bug spotted by Matt Ettus. sybreon 6280d 01h /aemb/branches/AEMB2_712/rtl/
31 Removed byte acrobatics. sybreon 6280d 01h /aemb/branches/AEMB2_712/rtl/
28 Fixed simulation bug. sybreon 6283d 01h /aemb/branches/AEMB2_712/rtl/
27 Removed some unnecessary bubble control. sybreon 6283d 12h /aemb/branches/AEMB2_712/rtl/

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