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[/] [aemb/] [branches/] [AEMB2_712/] [rtl/] [verilog/] - Rev 195

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Rev Log message Author Age Path
191 New directory structure. root 5608d 08h /aemb/branches/AEMB2_712/rtl/verilog/
77 This commit was manufactured by cvs2svn to create branch 'AEMB2_712'. 6066d 08h /aemb/branches/AEMB2_712/rtl/verilog/
76 initial sybreon 6066d 08h /aemb/branches/AEMB2_712/rtl/verilog/
73 Moved simulation kernel into code. sybreon 6073d 09h /aemb/branches/AEMB2_712/rtl/verilog/
72 Minor code cleanup. sybreon 6073d 10h /aemb/branches/AEMB2_712/rtl/verilog/
71 Old version deprecated. sybreon 6080d 12h /aemb/branches/AEMB2_712/rtl/verilog/
70 Change interrupt to positive level triggered interrupts. sybreon 6081d 11h /aemb/branches/AEMB2_712/rtl/verilog/
66 Added fsl_tag_o to FSL bus (tag either address or data). sybreon 6087d 05h /aemb/branches/AEMB2_712/rtl/verilog/
65 Fixed minor typo causing synthesis failure. sybreon 6088d 17h /aemb/branches/AEMB2_712/rtl/verilog/
63 Fixed interrupt signal synchronisation. sybreon 6089d 03h /aemb/branches/AEMB2_712/rtl/verilog/
62 Fixed minor typo. sybreon 6089d 03h /aemb/branches/AEMB2_712/rtl/verilog/
61 Changed interrupt handling system (reported by M. Ettus). sybreon 6089d 04h /aemb/branches/AEMB2_712/rtl/verilog/
56 Parameterised optional components into aeMB_xecu.v sybreon 6093d 02h /aemb/branches/AEMB2_712/rtl/verilog/
55 Upgraded license to LGPLv3.
Significant performance optimisations.		 sybreon 6093d 10h /aemb/branches/AEMB2_712/rtl/verilog/
53 Added GET/PUT support through a FSL bus. sybreon 6094d 06h /aemb/branches/AEMB2_712/rtl/verilog/
51 Fixed data WISHBONE arbitration problem (reported by J Lee). sybreon 6095d 09h /aemb/branches/AEMB2_712/rtl/verilog/
50 Parameterised optional components. sybreon 6095d 12h /aemb/branches/AEMB2_712/rtl/verilog/
48 Fixed spurious interrupt latching during long bus cycles (spotted by J Lee). sybreon 6099d 21h /aemb/branches/AEMB2_712/rtl/verilog/
45 Minor code cleanup. sybreon 6100d 18h /aemb/branches/AEMB2_712/rtl/verilog/
44 Added better (beta) interrupt support.
Changed MSR_IE to disabled at reset as per MB docs.		 sybreon 6101d 07h /aemb/branches/AEMB2_712/rtl/verilog/
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6101d 23h /aemb/branches/AEMB2_712/rtl/verilog/
39 Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. sybreon 6112d 07h /aemb/branches/AEMB2_712/rtl/verilog/
38 Added interrupt support. sybreon 6257d 08h /aemb/branches/AEMB2_712/rtl/verilog/
36 Removed asynchronous reset signal. sybreon 6270d 17h /aemb/branches/AEMB2_712/rtl/verilog/
35 Added async BRA/DLY signals for future clock, reset, and interrupt features. sybreon 6271d 14h /aemb/branches/AEMB2_712/rtl/verilog/
34 Corrected speed issues after rev 1.9 update. sybreon 6272d 04h /aemb/branches/AEMB2_712/rtl/verilog/
33 Fixed minor data hazard bug spotted by Matt Ettus. sybreon 6287d 11h /aemb/branches/AEMB2_712/rtl/verilog/
31 Removed byte acrobatics. sybreon 6287d 11h /aemb/branches/AEMB2_712/rtl/verilog/
28 Fixed simulation bug. sybreon 6290d 11h /aemb/branches/AEMB2_712/rtl/verilog/
27 Removed some unnecessary bubble control. sybreon 6290d 22h /aemb/branches/AEMB2_712/rtl/verilog/

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