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[/] [aemb/] [branches/] [AEMB2_712/] [sim/] - Rev 194

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Rev Log message Author Age Path
191 New directory structure. root 5590d 18h /aemb/branches/AEMB2_712/sim/
77 This commit was manufactured by cvs2svn to create branch 'AEMB2_712'. 6048d 18h /aemb/branches/AEMB2_712/sim/
73 Moved simulation kernel into code. sybreon 6055d 20h /aemb/branches/AEMB2_712/sim/
71 Old version deprecated. sybreon 6062d 23h /aemb/branches/AEMB2_712/sim/
69 Removed unnecessary byte acrobatics with VMEM data. sybreon 6065d 18h /aemb/branches/AEMB2_712/sim/
67 Minor simulation fixes. sybreon 6067d 17h /aemb/branches/AEMB2_712/sim/
59 Added posedge/negedge bus interface.
Modified interrupt test system.		 sybreon 6071d 15h /aemb/branches/AEMB2_712/sim/
58 Updated simulation to also check BRI 0x00 instruction. sybreon 6072d 13h /aemb/branches/AEMB2_712/sim/
53 Added GET/PUT support through a FSL bus. sybreon 6076d 16h /aemb/branches/AEMB2_712/sim/
52 Added log output to iverilog.log sybreon 6076d 16h /aemb/branches/AEMB2_712/sim/
50 Parameterised optional components. sybreon 6077d 22h /aemb/branches/AEMB2_712/sim/
49 Added random seed for simulation. sybreon 6081d 02h /aemb/branches/AEMB2_712/sim/
43 Added interrupt simulation.
Changed "human readable" simulation output.		 sybreon 6083d 17h /aemb/branches/AEMB2_712/sim/
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6084d 09h /aemb/branches/AEMB2_712/sim/
39 Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. sybreon 6094d 18h /aemb/branches/AEMB2_712/sim/
38 Added interrupt support. sybreon 6239d 18h /aemb/branches/AEMB2_712/sim/
31 Removed byte acrobatics. sybreon 6269d 21h /aemb/branches/AEMB2_712/sim/
30 Minor updates as sw/c/aeMB_testbench.c got updated. sybreon 6272d 21h /aemb/branches/AEMB2_712/sim/
22 Added support for 8-bit and 16-bit data types. sybreon 6274d 15h /aemb/branches/AEMB2_712/sim/
19 Added initial unified memory core. sybreon 6287d 00h /aemb/branches/AEMB2_712/sim/
18 Moved testbench into /sim/verilog.
Simulation cleanups.		 sybreon 6287d 16h /aemb/branches/AEMB2_712/sim/
15 Removed ROM file. Please generate it from the SW directory. sybreon 6295d 23h /aemb/branches/AEMB2_712/sim/
13 Fibonacci rom sybreon 6296d 06h /aemb/branches/AEMB2_712/sim/
2 initial import sybreon 6321d 19h /aemb/branches/AEMB2_712/sim/

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