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[/] [aemb/] [branches/] [DEV_SYBREON/] - Rev 70

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Rev Log message Author Age Path
70 Change interrupt to positive level triggered interrupts. sybreon 6095d 20h /aemb/branches/DEV_SYBREON/
69 Removed unnecessary byte acrobatics with VMEM data. sybreon 6097d 17h /aemb/branches/DEV_SYBREON/
68 Generate VMEM instead of HEX dumps of programme. sybreon 6097d 17h /aemb/branches/DEV_SYBREON/
67 Minor simulation fixes. sybreon 6099d 15h /aemb/branches/DEV_SYBREON/
66 Added fsl_tag_o to FSL bus (tag either address or data). sybreon 6101d 13h /aemb/branches/DEV_SYBREON/
65 Fixed minor typo causing synthesis failure. sybreon 6103d 02h /aemb/branches/DEV_SYBREON/
64 Fixed minor interrupt test typo. sybreon 6103d 11h /aemb/branches/DEV_SYBREON/
63 Fixed interrupt signal synchronisation. sybreon 6103d 12h /aemb/branches/DEV_SYBREON/
62 Fixed minor typo. sybreon 6103d 12h /aemb/branches/DEV_SYBREON/
61 Changed interrupt handling system (reported by M. Ettus). sybreon 6103d 13h /aemb/branches/DEV_SYBREON/
60 Added interrupt test routine. sybreon 6103d 13h /aemb/branches/DEV_SYBREON/
59 Added posedge/negedge bus interface.
Modified interrupt test system.		 sybreon 6103d 13h /aemb/branches/DEV_SYBREON/
58 Updated simulation to also check BRI 0x00 instruction. sybreon 6104d 12h /aemb/branches/DEV_SYBREON/
57 Updated documentation to EDK32 version. sybreon 6106d 13h /aemb/branches/DEV_SYBREON/
56 Parameterised optional components into aeMB_xecu.v sybreon 6107d 11h /aemb/branches/DEV_SYBREON/
55 Upgraded license to LGPLv3.
Significant performance optimisations.		 sybreon 6107d 19h /aemb/branches/DEV_SYBREON/
54 Added some compilation optimisations. sybreon 6108d 14h /aemb/branches/DEV_SYBREON/
53 Added GET/PUT support through a FSL bus. sybreon 6108d 14h /aemb/branches/DEV_SYBREON/
52 Added log output to iverilog.log sybreon 6108d 14h /aemb/branches/DEV_SYBREON/
51 Fixed data WISHBONE arbitration problem (reported by J Lee). sybreon 6109d 17h /aemb/branches/DEV_SYBREON/
50 Parameterised optional components. sybreon 6109d 21h /aemb/branches/DEV_SYBREON/
49 Added random seed for simulation. sybreon 6113d 00h /aemb/branches/DEV_SYBREON/
48 Fixed spurious interrupt latching during long bus cycles (spotted by J Lee). sybreon 6114d 06h /aemb/branches/DEV_SYBREON/
47 Added -msoft-float and -mxl-soft-div compiler flags. sybreon 6114d 06h /aemb/branches/DEV_SYBREON/
46 Minor code cleanup. sybreon 6115d 03h /aemb/branches/DEV_SYBREON/
45 Minor code cleanup. sybreon 6115d 03h /aemb/branches/DEV_SYBREON/
44 Added better (beta) interrupt support.
Changed MSR_IE to disabled at reset as per MB docs.		 sybreon 6115d 16h /aemb/branches/DEV_SYBREON/
43 Added interrupt simulation.
Changed "human readable" simulation output.		 sybreon 6115d 16h /aemb/branches/DEV_SYBREON/
42 Enable MSR_IE with software. sybreon 6115d 17h /aemb/branches/DEV_SYBREON/
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6116d 08h /aemb/branches/DEV_SYBREON/

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