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[/] [aemb/] [branches/] [DEV_SYBREON/] [rtl/] [verilog/] - Rev 100

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Rev Log message Author Age Path
100 multiplier issues sybreon 6033d 03h /aemb/branches/DEV_SYBREON/rtl/verilog/
99 Minor cleanup sybreon 6044d 22h /aemb/branches/DEV_SYBREON/rtl/verilog/
96 Stalls pipeline on MUL/BSF instructions results in minor speed improvements. sybreon 6048d 00h /aemb/branches/DEV_SYBREON/rtl/verilog/
95 Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. sybreon 6050d 02h /aemb/branches/DEV_SYBREON/rtl/verilog/
94 Prevent fHZD & rBRA[1] sybreon 6052d 00h /aemb/branches/DEV_SYBREON/rtl/verilog/
93 Minor enable fix sybreon 6052d 00h /aemb/branches/DEV_SYBREON/rtl/verilog/
92 Partitioned simulation model. sybreon 6055d 04h /aemb/branches/DEV_SYBREON/rtl/verilog/
91 Made idle thread PC track main PC. sybreon 6056d 10h /aemb/branches/DEV_SYBREON/rtl/verilog/
90 Fixed Carry bit bug. sybreon 6056d 10h /aemb/branches/DEV_SYBREON/rtl/verilog/
89 Changed simulation kernel. sybreon 6056d 10h /aemb/branches/DEV_SYBREON/rtl/verilog/
88 Minor optimisations. sybreon 6057d 02h /aemb/branches/DEV_SYBREON/rtl/verilog/
86 Some optimisations. sybreon 6057d 19h /aemb/branches/DEV_SYBREON/rtl/verilog/
85 Replaced OF/ID blocks with combined block. sybreon 6057d 19h /aemb/branches/DEV_SYBREON/rtl/verilog/
84 Added interrupt support. sybreon 6057d 19h /aemb/branches/DEV_SYBREON/rtl/verilog/
83 Combined ID/OF blocks. sybreon 6057d 19h /aemb/branches/DEV_SYBREON/rtl/verilog/
82 Further optimisations (speed + size). sybreon 6060d 01h /aemb/branches/DEV_SYBREON/rtl/verilog/
81 Code cleanup + minor speed regression. sybreon 6060d 02h /aemb/branches/DEV_SYBREON/rtl/verilog/
80 Minor optimisations (~10% faster) sybreon 6061d 03h /aemb/branches/DEV_SYBREON/rtl/verilog/
78 initial import sybreon 6062d 22h /aemb/branches/DEV_SYBREON/rtl/verilog/
76 initial sybreon 6066d 03h /aemb/branches/DEV_SYBREON/rtl/verilog/
73 Moved simulation kernel into code. sybreon 6073d 05h /aemb/branches/DEV_SYBREON/rtl/verilog/
72 Minor code cleanup. sybreon 6073d 06h /aemb/branches/DEV_SYBREON/rtl/verilog/
71 Old version deprecated. sybreon 6080d 08h /aemb/branches/DEV_SYBREON/rtl/verilog/
70 Change interrupt to positive level triggered interrupts. sybreon 6081d 07h /aemb/branches/DEV_SYBREON/rtl/verilog/
66 Added fsl_tag_o to FSL bus (tag either address or data). sybreon 6087d 01h /aemb/branches/DEV_SYBREON/rtl/verilog/
65 Fixed minor typo causing synthesis failure. sybreon 6088d 13h /aemb/branches/DEV_SYBREON/rtl/verilog/
63 Fixed interrupt signal synchronisation. sybreon 6088d 23h /aemb/branches/DEV_SYBREON/rtl/verilog/
62 Fixed minor typo. sybreon 6088d 23h /aemb/branches/DEV_SYBREON/rtl/verilog/
61 Changed interrupt handling system (reported by M. Ettus). sybreon 6089d 00h /aemb/branches/DEV_SYBREON/rtl/verilog/
56 Parameterised optional components into aeMB_xecu.v sybreon 6092d 22h /aemb/branches/DEV_SYBREON/rtl/verilog/

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