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[/] [aemb/] [branches/] [DEV_SYBREON/] [rtl/] [verilog/] - Rev 55

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Rev Log message Author Age Path
55 Upgraded license to LGPLv3.
Significant performance optimisations.		 sybreon 6110d 23h /aemb/branches/DEV_SYBREON/rtl/verilog/
53 Added GET/PUT support through a FSL bus. sybreon 6111d 19h /aemb/branches/DEV_SYBREON/rtl/verilog/
51 Fixed data WISHBONE arbitration problem (reported by J Lee). sybreon 6112d 22h /aemb/branches/DEV_SYBREON/rtl/verilog/
50 Parameterised optional components. sybreon 6113d 01h /aemb/branches/DEV_SYBREON/rtl/verilog/
48 Fixed spurious interrupt latching during long bus cycles (spotted by J Lee). sybreon 6117d 10h /aemb/branches/DEV_SYBREON/rtl/verilog/
45 Minor code cleanup. sybreon 6118d 07h /aemb/branches/DEV_SYBREON/rtl/verilog/
44 Added better (beta) interrupt support.
Changed MSR_IE to disabled at reset as per MB docs.		 sybreon 6118d 20h /aemb/branches/DEV_SYBREON/rtl/verilog/
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6119d 12h /aemb/branches/DEV_SYBREON/rtl/verilog/
39 Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. sybreon 6129d 20h /aemb/branches/DEV_SYBREON/rtl/verilog/
38 Added interrupt support. sybreon 6274d 21h /aemb/branches/DEV_SYBREON/rtl/verilog/
36 Removed asynchronous reset signal. sybreon 6288d 06h /aemb/branches/DEV_SYBREON/rtl/verilog/
35 Added async BRA/DLY signals for future clock, reset, and interrupt features. sybreon 6289d 03h /aemb/branches/DEV_SYBREON/rtl/verilog/
34 Corrected speed issues after rev 1.9 update. sybreon 6289d 17h /aemb/branches/DEV_SYBREON/rtl/verilog/
33 Fixed minor data hazard bug spotted by Matt Ettus. sybreon 6305d 00h /aemb/branches/DEV_SYBREON/rtl/verilog/
31 Removed byte acrobatics. sybreon 6305d 00h /aemb/branches/DEV_SYBREON/rtl/verilog/
28 Fixed simulation bug. sybreon 6308d 00h /aemb/branches/DEV_SYBREON/rtl/verilog/
27 Removed some unnecessary bubble control. sybreon 6308d 11h /aemb/branches/DEV_SYBREON/rtl/verilog/
26 Fixed minor synthesis bug. sybreon 6308d 11h /aemb/branches/DEV_SYBREON/rtl/verilog/
25 Added code documentation.
Improved size & speed of rtl/verilog/aeMB_aslu.v		 sybreon 6308d 15h /aemb/branches/DEV_SYBREON/rtl/verilog/
24 Made minor performance optimisations. sybreon 6309d 01h /aemb/branches/DEV_SYBREON/rtl/verilog/
23 Fixed minor simulation bug. sybreon 6309d 17h /aemb/branches/DEV_SYBREON/rtl/verilog/
22 Added support for 8-bit and 16-bit data types. sybreon 6309d 17h /aemb/branches/DEV_SYBREON/rtl/verilog/
19 Added initial unified memory core. sybreon 6322d 02h /aemb/branches/DEV_SYBREON/rtl/verilog/
18 Moved testbench into /sim/verilog.
Simulation cleanups.		 sybreon 6322d 19h /aemb/branches/DEV_SYBREON/rtl/verilog/
17 Cosmetic changes sybreon 6323d 23h /aemb/branches/DEV_SYBREON/rtl/verilog/
16 Added pipeline stalling from incomplete bus cycles.
Separated sync and async portions of code.		 sybreon 6324d 11h /aemb/branches/DEV_SYBREON/rtl/verilog/
14 Added initial interrupt/exception support. sybreon 6331d 01h /aemb/branches/DEV_SYBREON/rtl/verilog/
11 Removed unused signals sybreon 6331d 09h /aemb/branches/DEV_SYBREON/rtl/verilog/
10 Fixed minor bugs sybreon 6331d 09h /aemb/branches/DEV_SYBREON/rtl/verilog/
9 Extended testbench code sybreon 6331d 09h /aemb/branches/DEV_SYBREON/rtl/verilog/

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