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[/] [aemb/] [tags/] [AEMB_711/] [rtl/] - Rev 206

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Rev Log message Author Age Path
191 New directory structure. root 5590d 00h /aemb/tags/AEMB_711/rtl/
75 This commit was manufactured by cvs2svn to create tag 'AEMB_711'. 6055d 01h /aemb/tags/AEMB_711/rtl/
73 Moved simulation kernel into code. sybreon 6055d 01h /aemb/tags/AEMB_711/rtl/
72 Minor code cleanup. sybreon 6055d 02h /aemb/tags/AEMB_711/rtl/
71 Old version deprecated. sybreon 6062d 04h /aemb/tags/AEMB_711/rtl/
70 Change interrupt to positive level triggered interrupts. sybreon 6063d 03h /aemb/tags/AEMB_711/rtl/
66 Added fsl_tag_o to FSL bus (tag either address or data). sybreon 6068d 20h /aemb/tags/AEMB_711/rtl/
65 Fixed minor typo causing synthesis failure. sybreon 6070d 09h /aemb/tags/AEMB_711/rtl/
63 Fixed interrupt signal synchronisation. sybreon 6070d 19h /aemb/tags/AEMB_711/rtl/
62 Fixed minor typo. sybreon 6070d 19h /aemb/tags/AEMB_711/rtl/
61 Changed interrupt handling system (reported by M. Ettus). sybreon 6070d 20h /aemb/tags/AEMB_711/rtl/
56 Parameterised optional components into aeMB_xecu.v sybreon 6074d 18h /aemb/tags/AEMB_711/rtl/
55 Upgraded license to LGPLv3.
Significant performance optimisations.		 sybreon 6075d 02h /aemb/tags/AEMB_711/rtl/
53 Added GET/PUT support through a FSL bus. sybreon 6075d 21h /aemb/tags/AEMB_711/rtl/
51 Fixed data WISHBONE arbitration problem (reported by J Lee). sybreon 6077d 00h /aemb/tags/AEMB_711/rtl/
50 Parameterised optional components. sybreon 6077d 04h /aemb/tags/AEMB_711/rtl/
48 Fixed spurious interrupt latching during long bus cycles (spotted by J Lee). sybreon 6081d 13h /aemb/tags/AEMB_711/rtl/
45 Minor code cleanup. sybreon 6082d 10h /aemb/tags/AEMB_711/rtl/
44 Added better (beta) interrupt support.
Changed MSR_IE to disabled at reset as per MB docs.		 sybreon 6082d 23h /aemb/tags/AEMB_711/rtl/
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6083d 15h /aemb/tags/AEMB_711/rtl/
39 Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. sybreon 6093d 23h /aemb/tags/AEMB_711/rtl/
38 Added interrupt support. sybreon 6239d 00h /aemb/tags/AEMB_711/rtl/
36 Removed asynchronous reset signal. sybreon 6252d 09h /aemb/tags/AEMB_711/rtl/
35 Added async BRA/DLY signals for future clock, reset, and interrupt features. sybreon 6253d 06h /aemb/tags/AEMB_711/rtl/
34 Corrected speed issues after rev 1.9 update. sybreon 6253d 20h /aemb/tags/AEMB_711/rtl/
33 Fixed minor data hazard bug spotted by Matt Ettus. sybreon 6269d 02h /aemb/tags/AEMB_711/rtl/
31 Removed byte acrobatics. sybreon 6269d 02h /aemb/tags/AEMB_711/rtl/
28 Fixed simulation bug. sybreon 6272d 03h /aemb/tags/AEMB_711/rtl/
27 Removed some unnecessary bubble control. sybreon 6272d 14h /aemb/tags/AEMB_711/rtl/
26 Fixed minor synthesis bug. sybreon 6272d 14h /aemb/tags/AEMB_711/rtl/

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