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[/] [aemb/] [tags/] [AEMB_7_05/] [rtl/] [verilog/] - Rev 196

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Rev Log message Author Age Path
191 New directory structure. root 5608d 16h /aemb/tags/AEMB_7_05/rtl/verilog/
37 This commit was manufactured by cvs2svn to create tag 'AEMB_7_05'. 6271d 02h /aemb/tags/AEMB_7_05/rtl/verilog/
36 Removed asynchronous reset signal. sybreon 6271d 02h /aemb/tags/AEMB_7_05/rtl/verilog/
35 Added async BRA/DLY signals for future clock, reset, and interrupt features. sybreon 6271d 22h /aemb/tags/AEMB_7_05/rtl/verilog/
34 Corrected speed issues after rev 1.9 update. sybreon 6272d 12h /aemb/tags/AEMB_7_05/rtl/verilog/
33 Fixed minor data hazard bug spotted by Matt Ettus. sybreon 6287d 19h /aemb/tags/AEMB_7_05/rtl/verilog/
31 Removed byte acrobatics. sybreon 6287d 19h /aemb/tags/AEMB_7_05/rtl/verilog/
28 Fixed simulation bug. sybreon 6290d 19h /aemb/tags/AEMB_7_05/rtl/verilog/
27 Removed some unnecessary bubble control. sybreon 6291d 06h /aemb/tags/AEMB_7_05/rtl/verilog/
26 Fixed minor synthesis bug. sybreon 6291d 06h /aemb/tags/AEMB_7_05/rtl/verilog/
25 Added code documentation.
Improved size & speed of rtl/verilog/aeMB_aslu.v		 sybreon 6291d 10h /aemb/tags/AEMB_7_05/rtl/verilog/
24 Made minor performance optimisations. sybreon 6291d 20h /aemb/tags/AEMB_7_05/rtl/verilog/
23 Fixed minor simulation bug. sybreon 6292d 12h /aemb/tags/AEMB_7_05/rtl/verilog/
22 Added support for 8-bit and 16-bit data types. sybreon 6292d 12h /aemb/tags/AEMB_7_05/rtl/verilog/
19 Added initial unified memory core. sybreon 6304d 22h /aemb/tags/AEMB_7_05/rtl/verilog/
18 Moved testbench into /sim/verilog.
Simulation cleanups.		 sybreon 6305d 14h /aemb/tags/AEMB_7_05/rtl/verilog/
17 Cosmetic changes sybreon 6306d 18h /aemb/tags/AEMB_7_05/rtl/verilog/
16 Added pipeline stalling from incomplete bus cycles.
Separated sync and async portions of code.		 sybreon 6307d 06h /aemb/tags/AEMB_7_05/rtl/verilog/
14 Added initial interrupt/exception support. sybreon 6313d 21h /aemb/tags/AEMB_7_05/rtl/verilog/
11 Removed unused signals sybreon 6314d 04h /aemb/tags/AEMB_7_05/rtl/verilog/
10 Fixed minor bugs sybreon 6314d 04h /aemb/tags/AEMB_7_05/rtl/verilog/
9 Extended testbench code sybreon 6314d 04h /aemb/tags/AEMB_7_05/rtl/verilog/
8 Fixed memory read-write data hazard sybreon 6314d 04h /aemb/tags/AEMB_7_05/rtl/verilog/
7 Added CMP instruction sybreon 6314d 05h /aemb/tags/AEMB_7_05/rtl/verilog/
5 Fixed endian correction issues on data bus. sybreon 6314d 20h /aemb/tags/AEMB_7_05/rtl/verilog/
4 Fixed a minor bug where RD is trashed by a STORE instruction. Spotted by Joon Lee. sybreon 6322d 22h /aemb/tags/AEMB_7_05/rtl/verilog/
3 initial import sybreon 6339d 17h /aemb/tags/AEMB_7_05/rtl/verilog/

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