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[/] [aemb/] [trunk/] [rtl/] [verilog/] - Rev 147

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Rev Log message Author Age Path
147 Disconnect from pipeline. sybreon 5912d 00h /aemb/trunk/rtl/verilog/
140 Fixed minor typos. sybreon 5912d 01h /aemb/trunk/rtl/verilog/
134 Minor performance improvements. sybreon 5912d 23h /aemb/trunk/rtl/verilog/
132 Fixed minor typos. sybreon 5913d 15h /aemb/trunk/rtl/verilog/
131 Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor. sybreon 5913d 15h /aemb/trunk/rtl/verilog/
127 Fixed pipelined latching of data bug. sybreon 5916d 02h /aemb/trunk/rtl/verilog/
126 Fixed CMP bug. sybreon 5916d 02h /aemb/trunk/rtl/verilog/
125 Passes arithmetic tests with single thread. sybreon 5918d 04h /aemb/trunk/rtl/verilog/
124 FASM removed. sybreon 5918d 04h /aemb/trunk/rtl/verilog/
120 Basic version with some features left out. sybreon 5919d 00h /aemb/trunk/rtl/verilog/
119 Initial import. sybreon 5919d 00h /aemb/trunk/rtl/verilog/
118 Initial import. sybreon 5921d 16h /aemb/trunk/rtl/verilog/
114 changed MSR bits sybreon 5928d 01h /aemb/trunk/rtl/verilog/
105 Patch interrupt bug. sybreon 6009d 16h /aemb/trunk/rtl/verilog/
103 Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus) sybreon 6011d 01h /aemb/trunk/rtl/verilog/
102 Fix MTS during interrupt vectoring bug (reported by M. Ettus). sybreon 6011d 01h /aemb/trunk/rtl/verilog/
101 Made multiplier pause with pipeline sybreon 6020d 21h /aemb/trunk/rtl/verilog/
100 multiplier issues sybreon 6020d 21h /aemb/trunk/rtl/verilog/
99 Minor cleanup sybreon 6032d 16h /aemb/trunk/rtl/verilog/
96 Stalls pipeline on MUL/BSF instructions results in minor speed improvements. sybreon 6035d 18h /aemb/trunk/rtl/verilog/
95 Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. sybreon 6037d 20h /aemb/trunk/rtl/verilog/
94 Prevent fHZD & rBRA[1] sybreon 6039d 18h /aemb/trunk/rtl/verilog/
93 Minor enable fix sybreon 6039d 18h /aemb/trunk/rtl/verilog/
92 Partitioned simulation model. sybreon 6042d 22h /aemb/trunk/rtl/verilog/
91 Made idle thread PC track main PC. sybreon 6044d 04h /aemb/trunk/rtl/verilog/
90 Fixed Carry bit bug. sybreon 6044d 04h /aemb/trunk/rtl/verilog/
89 Changed simulation kernel. sybreon 6044d 04h /aemb/trunk/rtl/verilog/
88 Minor optimisations. sybreon 6044d 20h /aemb/trunk/rtl/verilog/
86 Some optimisations. sybreon 6045d 13h /aemb/trunk/rtl/verilog/
85 Replaced OF/ID blocks with combined block. sybreon 6045d 13h /aemb/trunk/rtl/verilog/

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