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[/] [aemb/] [trunk/] [rtl/] [verilog/] - Rev 202

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Rev Log message Author Age Path
202 added basic exception signals. sybreon 5494d 10h /aemb/trunk/rtl/verilog/
191 New directory structure. root 5624d 12h /aemb/trunk/rtl/verilog/
190 Housekeeping. sybreon 5638d 23h /aemb/trunk/rtl/verilog/
189 *** empty log message *** sybreon 5846d 22h /aemb/trunk/rtl/verilog/
188 *** empty log message *** sybreon 5846d 22h /aemb/trunk/rtl/verilog/
187 nc sybreon 5861d 10h /aemb/trunk/rtl/verilog/
186 added tool specific conditional defines. sybreon 5861d 10h /aemb/trunk/rtl/verilog/
172 single thread design sybreon 5900d 22h /aemb/trunk/rtl/verilog/
171 *** empty log message *** sybreon 5901d 09h /aemb/trunk/rtl/verilog/
170 initial sybreon 5901d 09h /aemb/trunk/rtl/verilog/
169 *** empty log message *** sybreon 5901d 10h /aemb/trunk/rtl/verilog/
168 *** empty log message *** sybreon 5901d 10h /aemb/trunk/rtl/verilog/
167 *** empty log message *** sybreon 5901d 10h /aemb/trunk/rtl/verilog/
166 final upload sybreon 5901d 10h /aemb/trunk/rtl/verilog/
160 minor typo. sybreon 5926d 17h /aemb/trunk/rtl/verilog/
159 Backported Adder from AEMB2_EDK62.
Fixes 64-bit math problem reported by M. Ettus.		 sybreon 5926d 17h /aemb/trunk/rtl/verilog/
158 Got rid of the Greater-Than comparator.
Other minor size optimisations.		 sybreon 5936d 19h /aemb/trunk/rtl/verilog/
157 Added interrupt capability. sybreon 5936d 22h /aemb/trunk/rtl/verilog/
150 Optimisations. sybreon 5939d 23h /aemb/trunk/rtl/verilog/
149 Minor performance optimisation. sybreon 5940d 06h /aemb/trunk/rtl/verilog/
148 added iwb_tag_o signal tied to MSR_ICE. sybreon 5940d 11h /aemb/trunk/rtl/verilog/
147 Disconnect from pipeline. sybreon 5940d 14h /aemb/trunk/rtl/verilog/
140 Fixed minor typos. sybreon 5940d 15h /aemb/trunk/rtl/verilog/
134 Minor performance improvements. sybreon 5941d 13h /aemb/trunk/rtl/verilog/
132 Fixed minor typos. sybreon 5942d 06h /aemb/trunk/rtl/verilog/
131 Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor. sybreon 5942d 06h /aemb/trunk/rtl/verilog/
127 Fixed pipelined latching of data bug. sybreon 5944d 17h /aemb/trunk/rtl/verilog/
126 Fixed CMP bug. sybreon 5944d 17h /aemb/trunk/rtl/verilog/
125 Passes arithmetic tests with single thread. sybreon 5946d 19h /aemb/trunk/rtl/verilog/
124 FASM removed. sybreon 5946d 19h /aemb/trunk/rtl/verilog/

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