OpenCores
URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [rtl/] [verilog/] - Rev 204

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
204 added initial exception handler in the pipeline. sybreon 5454d 03h /aemb/trunk/rtl/verilog/
203 optimised exception signals. sybreon 5454d 03h /aemb/trunk/rtl/verilog/
202 added basic exception signals. sybreon 5454d 03h /aemb/trunk/rtl/verilog/
191 New directory structure. root 5584d 06h /aemb/trunk/rtl/verilog/
190 Housekeeping. sybreon 5598d 16h /aemb/trunk/rtl/verilog/
189 *** empty log message *** sybreon 5806d 16h /aemb/trunk/rtl/verilog/
188 *** empty log message *** sybreon 5806d 16h /aemb/trunk/rtl/verilog/
187 nc sybreon 5821d 03h /aemb/trunk/rtl/verilog/
186 added tool specific conditional defines. sybreon 5821d 03h /aemb/trunk/rtl/verilog/
172 single thread design sybreon 5860d 15h /aemb/trunk/rtl/verilog/
171 *** empty log message *** sybreon 5861d 03h /aemb/trunk/rtl/verilog/
170 initial sybreon 5861d 03h /aemb/trunk/rtl/verilog/
169 *** empty log message *** sybreon 5861d 04h /aemb/trunk/rtl/verilog/
168 *** empty log message *** sybreon 5861d 04h /aemb/trunk/rtl/verilog/
167 *** empty log message *** sybreon 5861d 04h /aemb/trunk/rtl/verilog/
166 final upload sybreon 5861d 04h /aemb/trunk/rtl/verilog/
160 minor typo. sybreon 5886d 11h /aemb/trunk/rtl/verilog/
159 Backported Adder from AEMB2_EDK62.
Fixes 64-bit math problem reported by M. Ettus.		 sybreon 5886d 11h /aemb/trunk/rtl/verilog/
158 Got rid of the Greater-Than comparator.
Other minor size optimisations.		 sybreon 5896d 13h /aemb/trunk/rtl/verilog/
157 Added interrupt capability. sybreon 5896d 16h /aemb/trunk/rtl/verilog/
150 Optimisations. sybreon 5899d 16h /aemb/trunk/rtl/verilog/
149 Minor performance optimisation. sybreon 5900d 00h /aemb/trunk/rtl/verilog/
148 added iwb_tag_o signal tied to MSR_ICE. sybreon 5900d 05h /aemb/trunk/rtl/verilog/
147 Disconnect from pipeline. sybreon 5900d 08h /aemb/trunk/rtl/verilog/
140 Fixed minor typos. sybreon 5900d 09h /aemb/trunk/rtl/verilog/
134 Minor performance improvements. sybreon 5901d 07h /aemb/trunk/rtl/verilog/
132 Fixed minor typos. sybreon 5901d 23h /aemb/trunk/rtl/verilog/
131 Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor. sybreon 5902d 00h /aemb/trunk/rtl/verilog/
127 Fixed pipelined latching of data bug. sybreon 5904d 10h /aemb/trunk/rtl/verilog/
126 Fixed CMP bug. sybreon 5904d 10h /aemb/trunk/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.