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[/] [aemb/] [trunk/] [rtl/] [verilog/] - Rev 91

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Rev Log message Author Age Path
91 Made idle thread PC track main PC. sybreon 6044d 10h /aemb/trunk/rtl/verilog/
90 Fixed Carry bit bug. sybreon 6044d 10h /aemb/trunk/rtl/verilog/
89 Changed simulation kernel. sybreon 6044d 10h /aemb/trunk/rtl/verilog/
88 Minor optimisations. sybreon 6045d 02h /aemb/trunk/rtl/verilog/
86 Some optimisations. sybreon 6045d 20h /aemb/trunk/rtl/verilog/
85 Replaced OF/ID blocks with combined block. sybreon 6045d 20h /aemb/trunk/rtl/verilog/
84 Added interrupt support. sybreon 6045d 20h /aemb/trunk/rtl/verilog/
83 Combined ID/OF blocks. sybreon 6045d 20h /aemb/trunk/rtl/verilog/
82 Further optimisations (speed + size). sybreon 6048d 02h /aemb/trunk/rtl/verilog/
81 Code cleanup + minor speed regression. sybreon 6048d 03h /aemb/trunk/rtl/verilog/
80 Minor optimisations (~10% faster) sybreon 6049d 04h /aemb/trunk/rtl/verilog/
78 initial import sybreon 6050d 22h /aemb/trunk/rtl/verilog/
76 initial sybreon 6054d 04h /aemb/trunk/rtl/verilog/
73 Moved simulation kernel into code. sybreon 6061d 06h /aemb/trunk/rtl/verilog/
72 Minor code cleanup. sybreon 6061d 06h /aemb/trunk/rtl/verilog/
71 Old version deprecated. sybreon 6068d 09h /aemb/trunk/rtl/verilog/
70 Change interrupt to positive level triggered interrupts. sybreon 6069d 08h /aemb/trunk/rtl/verilog/
66 Added fsl_tag_o to FSL bus (tag either address or data). sybreon 6075d 01h /aemb/trunk/rtl/verilog/
65 Fixed minor typo causing synthesis failure. sybreon 6076d 14h /aemb/trunk/rtl/verilog/
63 Fixed interrupt signal synchronisation. sybreon 6076d 23h /aemb/trunk/rtl/verilog/
62 Fixed minor typo. sybreon 6077d 00h /aemb/trunk/rtl/verilog/
61 Changed interrupt handling system (reported by M. Ettus). sybreon 6077d 01h /aemb/trunk/rtl/verilog/
56 Parameterised optional components into aeMB_xecu.v sybreon 6080d 23h /aemb/trunk/rtl/verilog/
55 Upgraded license to LGPLv3.
Significant performance optimisations.		 sybreon 6081d 06h /aemb/trunk/rtl/verilog/
53 Added GET/PUT support through a FSL bus. sybreon 6082d 02h /aemb/trunk/rtl/verilog/
51 Fixed data WISHBONE arbitration problem (reported by J Lee). sybreon 6083d 05h /aemb/trunk/rtl/verilog/
50 Parameterised optional components. sybreon 6083d 09h /aemb/trunk/rtl/verilog/
48 Fixed spurious interrupt latching during long bus cycles (spotted by J Lee). sybreon 6087d 18h /aemb/trunk/rtl/verilog/
45 Minor code cleanup. sybreon 6088d 14h /aemb/trunk/rtl/verilog/
44 Added better (beta) interrupt support.
Changed MSR_IE to disabled at reset as per MB docs.		 sybreon 6089d 04h /aemb/trunk/rtl/verilog/

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