OpenCores
URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [sim/] - Rev 208

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
208 removed illegal read/write messages due to misaligned memory exception tests. sybreon 5490d 05h /aemb/trunk/sim/
206 partially working exceptions. sybreon 5490d 05h /aemb/trunk/sim/
191 New directory structure. root 5620d 08h /aemb/trunk/sim/
164 added random seed sybreon 5903d 12h /trunk/sim/
163 updated to new iversim compatibility sybreon 5903d 12h /trunk/sim/
162 Modified script to use verilog pre-processing.
Changed /bin/bash to /bin/sh as suggested by "Wojciech A. Koszek" <wkoszek@freebsd.org> for FreeBSD compatibility.
sybreon 5906d 08h /trunk/sim/
157 Added interrupt capability. sybreon 5932d 18h /trunk/sim/
156 initial import sybreon 5932d 18h /trunk/sim/
155 Minor cosmetic changes. sybreon 5932d 18h /trunk/sim/
144 Added VCD2LXT functions. sybreon 5936d 10h /trunk/sim/
143 Fixed minor typos. sybreon 5936d 10h /trunk/sim/
138 initial import sybreon 5937d 08h /trunk/sim/
98 Minor typo sybreon 6057d 05h /trunk/sim/
95 Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. sybreon 6062d 06h /trunk/sim/
92 Partitioned simulation model. sybreon 6067d 08h /trunk/sim/
79 Modified for AEMB2 sybreon 6075d 02h /trunk/sim/
73 Moved simulation kernel into code. sybreon 6085d 09h /trunk/sim/
71 Old version deprecated. sybreon 6092d 12h /trunk/sim/
69 Removed unnecessary byte acrobatics with VMEM data. sybreon 6095d 08h /trunk/sim/
67 Minor simulation fixes. sybreon 6097d 07h /trunk/sim/
59 Added posedge/negedge bus interface.
Modified interrupt test system.
sybreon 6101d 04h /trunk/sim/
58 Updated simulation to also check BRI 0x00 instruction. sybreon 6102d 03h /trunk/sim/
53 Added GET/PUT support through a FSL bus. sybreon 6106d 06h /trunk/sim/
52 Added log output to iverilog.log sybreon 6106d 06h /trunk/sim/
50 Parameterised optional components. sybreon 6107d 12h /trunk/sim/
49 Added random seed for simulation. sybreon 6110d 16h /trunk/sim/
43 Added interrupt simulation.
Changed "human readable" simulation output.
sybreon 6113d 07h /trunk/sim/
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.
sybreon 6113d 23h /trunk/sim/
39 Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. sybreon 6124d 07h /trunk/sim/
38 Added interrupt support. sybreon 6269d 08h /trunk/sim/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.