OpenCores
URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [sim/] [verilog/] - Rev 202

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
191 New directory structure. root 5590d 09h /aemb/trunk/sim/verilog/
164 added random seed sybreon 5873d 13h /aemb/trunk/sim/verilog/
163 updated to new iversim compatibility sybreon 5873d 13h /aemb/trunk/sim/verilog/
157 Added interrupt capability. sybreon 5902d 19h /aemb/trunk/sim/verilog/
143 Fixed minor typos. sybreon 5906d 11h /aemb/trunk/sim/verilog/
138 initial import sybreon 5907d 09h /aemb/trunk/sim/verilog/
98 Minor typo sybreon 6027d 06h /aemb/trunk/sim/verilog/
95 Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. sybreon 6032d 07h /aemb/trunk/sim/verilog/
92 Partitioned simulation model. sybreon 6037d 08h /aemb/trunk/sim/verilog/
79 Modified for AEMB2 sybreon 6045d 03h /aemb/trunk/sim/verilog/
73 Moved simulation kernel into code. sybreon 6055d 10h /aemb/trunk/sim/verilog/
71 Old version deprecated. sybreon 6062d 13h /aemb/trunk/sim/verilog/
69 Removed unnecessary byte acrobatics with VMEM data. sybreon 6065d 09h /aemb/trunk/sim/verilog/
67 Minor simulation fixes. sybreon 6067d 08h /aemb/trunk/sim/verilog/
59 Added posedge/negedge bus interface.
Modified interrupt test system.		 sybreon 6071d 05h /aemb/trunk/sim/verilog/
58 Updated simulation to also check BRI 0x00 instruction. sybreon 6072d 04h /aemb/trunk/sim/verilog/
53 Added GET/PUT support through a FSL bus. sybreon 6076d 06h /aemb/trunk/sim/verilog/
50 Parameterised optional components. sybreon 6077d 13h /aemb/trunk/sim/verilog/
49 Added random seed for simulation. sybreon 6080d 16h /aemb/trunk/sim/verilog/
43 Added interrupt simulation.
Changed "human readable" simulation output.		 sybreon 6083d 08h /aemb/trunk/sim/verilog/
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6084d 00h /aemb/trunk/sim/verilog/
39 Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. sybreon 6094d 08h /aemb/trunk/sim/verilog/
38 Added interrupt support. sybreon 6239d 09h /aemb/trunk/sim/verilog/
31 Removed byte acrobatics. sybreon 6269d 11h /aemb/trunk/sim/verilog/
30 Minor updates as sw/c/aeMB_testbench.c got updated. sybreon 6272d 12h /aemb/trunk/sim/verilog/
22 Added support for 8-bit and 16-bit data types. sybreon 6274d 05h /aemb/trunk/sim/verilog/
19 Added initial unified memory core. sybreon 6286d 14h /aemb/trunk/sim/verilog/
18 Moved testbench into /sim/verilog.
Simulation cleanups.		 sybreon 6287d 07h /aemb/trunk/sim/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.