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[/] [aemb/] [trunk/] [sim/] [verilog/] - Rev 206

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Rev Log message Author Age Path
206 partially working exceptions. sybreon 5468d 06h /aemb/trunk/sim/verilog/
191 New directory structure. root 5598d 09h /aemb/trunk/sim/verilog/
164 added random seed sybreon 5881d 14h /aemb/trunk/sim/verilog/
163 updated to new iversim compatibility sybreon 5881d 14h /aemb/trunk/sim/verilog/
157 Added interrupt capability. sybreon 5910d 19h /aemb/trunk/sim/verilog/
143 Fixed minor typos. sybreon 5914d 11h /aemb/trunk/sim/verilog/
138 initial import sybreon 5915d 09h /aemb/trunk/sim/verilog/
98 Minor typo sybreon 6035d 06h /aemb/trunk/sim/verilog/
95 Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. sybreon 6040d 07h /aemb/trunk/sim/verilog/
92 Partitioned simulation model. sybreon 6045d 09h /aemb/trunk/sim/verilog/
79 Modified for AEMB2 sybreon 6053d 03h /aemb/trunk/sim/verilog/
73 Moved simulation kernel into code. sybreon 6063d 10h /aemb/trunk/sim/verilog/
71 Old version deprecated. sybreon 6070d 13h /aemb/trunk/sim/verilog/
69 Removed unnecessary byte acrobatics with VMEM data. sybreon 6073d 09h /aemb/trunk/sim/verilog/
67 Minor simulation fixes. sybreon 6075d 08h /aemb/trunk/sim/verilog/
59 Added posedge/negedge bus interface.
Modified interrupt test system.		 sybreon 6079d 05h /aemb/trunk/sim/verilog/
58 Updated simulation to also check BRI 0x00 instruction. sybreon 6080d 04h /aemb/trunk/sim/verilog/
53 Added GET/PUT support through a FSL bus. sybreon 6084d 07h /aemb/trunk/sim/verilog/
50 Parameterised optional components. sybreon 6085d 13h /aemb/trunk/sim/verilog/
49 Added random seed for simulation. sybreon 6088d 17h /aemb/trunk/sim/verilog/
43 Added interrupt simulation.
Changed "human readable" simulation output.		 sybreon 6091d 08h /aemb/trunk/sim/verilog/
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6092d 00h /aemb/trunk/sim/verilog/
39 Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. sybreon 6102d 08h /aemb/trunk/sim/verilog/
38 Added interrupt support. sybreon 6247d 09h /aemb/trunk/sim/verilog/
31 Removed byte acrobatics. sybreon 6277d 12h /aemb/trunk/sim/verilog/
30 Minor updates as sw/c/aeMB_testbench.c got updated. sybreon 6280d 12h /aemb/trunk/sim/verilog/
22 Added support for 8-bit and 16-bit data types. sybreon 6282d 05h /aemb/trunk/sim/verilog/
19 Added initial unified memory core. sybreon 6294d 15h /aemb/trunk/sim/verilog/
18 Moved testbench into /sim/verilog.
Simulation cleanups.		 sybreon 6295d 07h /aemb/trunk/sim/verilog/

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