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[/] [axi4_tlm_bfm/] [trunk/] - Rev 21

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21 Added synthesis files for Vivado. The RTL have not yet been updated with the latest changes available in the Quartus version. daniel.kho 3813d 10h /axi4_tlm_bfm/trunk/
20 Updated simulation scripts. daniel.kho 3813d 10h /axi4_tlm_bfm/trunk/
19 Updated synthesis constraints and scripts. daniel.kho 3813d 10h /axi4_tlm_bfm/trunk/
18 Added hardware PRBS generator, modularised top-level by having separate file as the tester. daniel.kho 3813d 10h /axi4_tlm_bfm/trunk/
17 Added more pipelining, enhancements. Tested on BeMicro kit. daniel.kho 3813d 10h /axi4_tlm_bfm/trunk/
16 Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input. daniel.kho 3916d 06h /axi4_tlm_bfm/trunk/
15 [minor]: cleaned up sources. daniel.kho 3918d 13h /axi4_tlm_bfm/trunk/
14 Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap. daniel.kho 3927d 03h /axi4_tlm_bfm/trunk/
13 Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. daniel.kho 3927d 08h /axi4_tlm_bfm/trunk/
12 Used generic package instead of using tauhop.tlm (abstract package) directly, and updated corresponding context paths. Simulated fine with ModelSim 10.1b. [previous]: Previous update included synthesis fixes ported from simulation sources. daniel.kho 3936d 12h /axi4_tlm_bfm/trunk/
11 Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match. daniel.kho 3938d 06h /axi4_tlm_bfm/trunk/
10 Written a few more directed testcases (in user.vhdl), and fixed several bugs. TODO move the testcases to the stimuli folder. daniel.kho 3942d 07h /axi4_tlm_bfm/trunk/
9 Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages. daniel.kho 3945d 03h /axi4_tlm_bfm/trunk/
8 [minor]: removed writeStream(). The write() procedure can be used for both stream and non-stream interfaces. For stream interfaces, just map the address argument to don't-cares. Made several other minor enhancements, simplifications. daniel.kho 4045d 08h /axi4_tlm_bfm/trunk/
7 [minor]: renamed axi4-stream-bfm.vhdl to axi4-stream-bfm-master.vhdl so as to allow a future implementation of the AXI4-Stream slave / receiver. Changed simulation script to start GUI simulation only when there are no errors (previously, it brings up the GUI even when there are compilation errors). daniel.kho 4049d 03h /axi4_tlm_bfm/trunk/
6 [minor]: expanded some waveforms and show random stimulus from simulation script. daniel.kho 4049d 07h /axi4_tlm_bfm/trunk/
5 [minor]: refactored type names to use the convention 't_*' for more clarity. AXI4-Stream signal names also starts with a 't'. daniel.kho 4049d 11h /axi4_tlm_bfm/trunk/
4 [minor]: Removed unused libraries from simulation script. daniel.kho 4050d 05h /axi4_tlm_bfm/trunk/
3 Updated user.vhdl to use math_real's uniform for testbench randomisation. This is to avoid having to include third-party libraries into the project. Simulation of user.vhdl works - writeStream() procedure is used to send AXI4-Stream bus writes. More verification will follow. daniel.kho 4050d 06h /axi4_tlm_bfm/trunk/
2 Initial commit.
Added packages and usage example for AXI4-Stream protocol.
Added simulation scripts for ModelSim/QuestaSim.		 daniel.kho 4050d 16h /axi4_tlm_bfm/trunk/
1 The project and the structure was created root 4051d 03h /axi4_tlm_bfm/trunk/

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