| Rev |
Log message |
Author |
Age |
Path |
| 42 |
Major enhancements and bugfix. Used DDR for AXI BFM for enhanced functionality and performance. Tested in simulation; TODO update synthesis design files. |
daniel.kho |
3764d 01h |
/axi4_tlm_bfm/trunk/rtl/ |
| 39 |
Deprecated symbolsPerTransfer and outstandingTransactions; replaced with lastTransaction. Fixed small bug in BFM; tData and tValid should be valid even for the last transaction. |
daniel.kho |
3775d 09h |
/axi4_tlm_bfm/trunk/rtl/ |
| 36 |
Added missing pkg-types.vhdl file for simulation. |
daniel.kho |
3821d 22h |
/axi4_tlm_bfm/trunk/rtl/ |
| 25 |
Refactored folders. |
daniel.kho |
3841d 08h |
/axi4_tlm_bfm/trunk/rtl/ |
| 24 |
Updated simulation sources to reflect changes made for synthesis. |
daniel.kho |
3841d 08h |
/axi4_tlm_bfm/trunk/rtl/ |
| 23 |
Added top-level user example used in technical paper. |
daniel.kho |
3849d 02h |
/axi4_tlm_bfm/trunk/rtl/ |
| 21 |
Added synthesis files for Vivado. The RTL have not yet been updated with the latest changes available in the Quartus version. |
daniel.kho |
3852d 04h |
/axi4_tlm_bfm/trunk/rtl/ |
| 18 |
Added hardware PRBS generator, modularised top-level by having separate file as the tester. |
daniel.kho |
3852d 04h |
/axi4_tlm_bfm/trunk/rtl/ |
| 17 |
Added more pipelining, enhancements. Tested on BeMicro kit. |
daniel.kho |
3852d 05h |
/axi4_tlm_bfm/trunk/rtl/ |
| 16 |
Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input. |
daniel.kho |
3955d 01h |
/axi4_tlm_bfm/trunk/rtl/ |
| 15 |
[minor]: cleaned up sources. |
daniel.kho |
3957d 07h |
/axi4_tlm_bfm/trunk/rtl/ |
| 14 |
Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap. |
daniel.kho |
3965d 22h |
/axi4_tlm_bfm/trunk/rtl/ |
| 13 |
Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. |
daniel.kho |
3966d 02h |
/axi4_tlm_bfm/trunk/rtl/ |
| 12 |
Used generic package instead of using tauhop.tlm (abstract package) directly, and updated corresponding context paths. Simulated fine with ModelSim 10.1b. [previous]: Previous update included synthesis fixes ported from simulation sources. |
daniel.kho |
3975d 06h |
/axi4_tlm_bfm/trunk/rtl/ |
| 11 |
Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match. |
daniel.kho |
3977d 01h |
/axi4_tlm_bfm/trunk/rtl/ |
| 10 |
Written a few more directed testcases (in user.vhdl), and fixed several bugs. TODO move the testcases to the stimuli folder. |
daniel.kho |
3981d 01h |
/axi4_tlm_bfm/trunk/rtl/ |
| 9 |
Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages. |
daniel.kho |
3983d 21h |
/axi4_tlm_bfm/trunk/rtl/ |
| 8 |
[minor]: removed writeStream(). The write() procedure can be used for both stream and non-stream interfaces. For stream interfaces, just map the address argument to don't-cares. Made several other minor enhancements, simplifications. |
daniel.kho |
4084d 03h |
/axi4_tlm_bfm/trunk/rtl/ |
| 7 |
[minor]: renamed axi4-stream-bfm.vhdl to axi4-stream-bfm-master.vhdl so as to allow a future implementation of the AXI4-Stream slave / receiver. Changed simulation script to start GUI simulation only when there are no errors (previously, it brings up the GUI even when there are compilation errors). |
daniel.kho |
4087d 21h |
/axi4_tlm_bfm/trunk/rtl/ |
| 6 |
[minor]: expanded some waveforms and show random stimulus from simulation script. |
daniel.kho |
4088d 02h |
/axi4_tlm_bfm/trunk/rtl/ |
| 5 |
[minor]: refactored type names to use the convention 't_*' for more clarity. AXI4-Stream signal names also starts with a 't'. |
daniel.kho |
4088d 06h |
/axi4_tlm_bfm/trunk/rtl/ |
| 3 |
Updated user.vhdl to use math_real's uniform for testbench randomisation. This is to avoid having to include third-party libraries into the project. Simulation of user.vhdl works - writeStream() procedure is used to send AXI4-Stream bus writes. More verification will follow. |
daniel.kho |
4089d 01h |
/axi4_tlm_bfm/trunk/rtl/ |
| 2 |
Initial commit.
Added packages and usage example for AXI4-Stream protocol.
Added simulation scripts for ModelSim/QuestaSim. |
daniel.kho |
4089d 11h |
/axi4_tlm_bfm/trunk/rtl/ |
