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Rev Log message Author Age Path
38 Temporary backup version (still fully operable). mohor 7849d 06h /can/tags/rel_12/bench/verilog/
37 Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted. mohor 7849d 06h /can/tags/rel_12/bench/verilog/
35 Several registers added. Not finished, yet. mohor 7852d 10h /can/tags/rel_12/bench/verilog/
34 Errors monitoring improved. arbitration_lost improved. mohor 7854d 16h /can/tags/rel_12/bench/verilog/
31 Wishbone interface added. mohor 7856d 06h /can/tags/rel_12/bench/verilog/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7857d 12h /can/tags/rel_12/bench/verilog/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7858d 04h /can/tags/rel_12/bench/verilog/
26 Backup. mohor 7862d 13h /can/tags/rel_12/bench/verilog/
25 *** empty log message *** mohor 7862d 16h /can/tags/rel_12/bench/verilog/
24 backup. mohor 7867d 05h /can/tags/rel_12/bench/verilog/
22 Form error supported. When receiving messages, last bit of the end-of-frame
does not generate form error. Receiver goes to the idle mode one bit sooner.
(CAN specification ver 2.0, part B, page 57).		 mohor 7881d 17h /can/tags/rel_12/bench/verilog/
20 CRC checking fixed (when bitstuff occurs at the end of a CRC sequence). mohor 7882d 09h /can/tags/rel_12/bench/verilog/
19 RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received. mohor 7882d 16h /can/tags/rel_12/bench/verilog/
18 When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. mohor 7882d 17h /can/tags/rel_12/bench/verilog/
17 Addresses corrected to decimal values (previously hex). mohor 7883d 13h /can/tags/rel_12/bench/verilog/
16 rx_fifo is now working. mohor 7883d 18h /can/tags/rel_12/bench/verilog/
15 Temporary version (backup). mohor 7887d 13h /can/tags/rel_12/bench/verilog/
14 rx fifo added. Not 100 % verified, yet. mohor 7888d 09h /can/tags/rel_12/bench/verilog/
13 Temporary files (backup). mohor 7888d 16h /can/tags/rel_12/bench/verilog/
11 Acceptance filter added. mohor 7890d 04h /can/tags/rel_12/bench/verilog/
10 Backup version. mohor 7901d 02h /can/tags/rel_12/bench/verilog/
9 Header changed, testbench improved to send a frame (crc still missing). mohor 7902d 06h /can/tags/rel_12/bench/verilog/
8 Testbench define file added. Clock divider register added. mohor 7902d 15h /can/tags/rel_12/bench/verilog/
7 Tripple sampling supported. mohor 7903d 05h /can/tags/rel_12/bench/verilog/
6 Commented lines removed. mohor 7903d 07h /can/tags/rel_12/bench/verilog/
5 Synchronization working. mohor 7903d 16h /can/tags/rel_12/bench/verilog/
2 Initial mohor 7908d 14h /can/tags/rel_12/bench/verilog/

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