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Rev Log message Author Age Path
161 New directory structure. root 5637d 03h /can/tags/rel_12/rtl/verilog/
113 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7698d 08h /can/tags/rel_12/rtl/verilog/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7698d 08h /can/tags/rel_12/rtl/verilog/
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7700d 08h /can/tags/rel_12/rtl/verilog/
110 Fixed according to the linter. mohor 7700d 08h /can/tags/rel_12/rtl/verilog/
109 Fixed according to the linter. mohor 7700d 09h /can/tags/rel_12/rtl/verilog/
108 Fixed according to the linter. mohor 7700d 09h /can/tags/rel_12/rtl/verilog/
107 Fixed according to the linter. mohor 7700d 10h /can/tags/rel_12/rtl/verilog/
106 Unused signal removed. mohor 7706d 07h /can/tags/rel_12/rtl/verilog/
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7706d 21h /can/tags/rel_12/rtl/verilog/
102 Little fixes (to fix warnings). mohor 7709d 12h /can/tags/rel_12/rtl/verilog/
100 Synchronization changed. mohor 7713d 13h /can/tags/rel_12/rtl/verilog/
99 PCI_BIST replaced with CAN_BIST. mohor 7713d 13h /can/tags/rel_12/rtl/verilog/
97 Overrun fifo implemented with FFs, because it is not possible to create such a memory. simons 7719d 01h /can/tags/rel_12/rtl/verilog/
95 Virtual silicon ram instances added. simons 7719d 02h /can/tags/rel_12/rtl/verilog/
93 synthesis full_case parallel_case fixed. mohor 7724d 13h /can/tags/rel_12/rtl/verilog/
92 clkout is clk/2 after the reset. mohor 7724d 21h /can/tags/rel_12/rtl/verilog/
90 paralel_case and full_case compiler directives added to case statements. mohor 7725d 11h /can/tags/rel_12/rtl/verilog/
88 Previous change removed. When resynchronization occurs we go to seg1
stage. sync stage does not cause another start of seg1 stage.		 mohor 7726d 08h /can/tags/rel_12/rtl/verilog/
87 When hard_sync or resync occure we need to go to seg1 segment. Going to
sync segment is in that case blocked.		 mohor 7726d 08h /can/tags/rel_12/rtl/verilog/
85 Typo fixed. mohor 7728d 00h /can/tags/rel_12/rtl/verilog/
84 clk_cnt reduced from [8:0] to [6:0]. mohor 7729d 07h /can/tags/rel_12/rtl/verilog/
82 Removed few signals. mohor 7729d 08h /can/tags/rel_12/rtl/verilog/
81 "chip select" signal cs_can_i is used only when not using WISHBONE
interface.		 mohor 7729d 08h /can/tags/rel_12/rtl/verilog/
80 Form error was detected when stuff bit occured at the end of crc. mohor 7729d 08h /can/tags/rel_12/rtl/verilog/
79 Bit stuffing corrected when stuffing comes at the end of the crc. tadejm 7730d 08h /can/tags/rel_12/rtl/verilog/
78 tx_point generated one clk earlier. rx_i registered. Data corrected when
using extended mode.		 mohor 7730d 09h /can/tags/rel_12/rtl/verilog/
77 Synchronization is also needed when transmitting a message. mohor 7733d 08h /can/tags/rel_12/rtl/verilog/
76 Counters width changed. mohor 7733d 08h /can/tags/rel_12/rtl/verilog/
75 When switching to tx, sync stage is overjumped. mohor 7735d 09h /can/tags/rel_12/rtl/verilog/

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