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[/] [can/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 82

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Rev	Log message	Author	Age	Path
82	Removed few signals.	mohor	7729d 20h	/can/tags/rel_12/rtl/verilog/
81	"chip select" signal cs_can_i is used only when not using WISHBONE interface.	mohor	7729d 20h	/can/tags/rel_12/rtl/verilog/
80	Form error was detected when stuff bit occured at the end of crc.	mohor	7729d 20h	/can/tags/rel_12/rtl/verilog/
79	Bit stuffing corrected when stuffing comes at the end of the crc.	tadejm	7730d 20h	/can/tags/rel_12/rtl/verilog/
78	tx_point generated one clk earlier. rx_i registered. Data corrected when using extended mode.	mohor	7730d 20h	/can/tags/rel_12/rtl/verilog/
77	Synchronization is also needed when transmitting a message.	mohor	7733d 19h	/can/tags/rel_12/rtl/verilog/
76	Counters width changed.	mohor	7733d 20h	/can/tags/rel_12/rtl/verilog/
75	When switching to tx, sync stage is overjumped.	mohor	7735d 20h	/can/tags/rel_12/rtl/verilog/
73	overrun and length_info fifos are initialized at the end of reset.	mohor	7736d 01h	/can/tags/rel_12/rtl/verilog/
71	Ports added for the CAN_BIST.	mohor	7737d 23h	/can/tags/rel_12/rtl/verilog/
70	data_out is already registered in the can_top.v file.	mohor	7737d 23h	/can/tags/rel_12/rtl/verilog/
69	Some features are supported in extended mode only (listen_only_mode...).	mohor	7792d 19h	/can/tags/rel_12/rtl/verilog/
67	CAN interrupt is active low.	mohor	7812d 23h	/can/tags/rel_12/rtl/verilog/
66	unix.	mohor	7818d 17h	/can/tags/rel_12/rtl/verilog/
65	unix.	mohor	7818d 17h	/can/tags/rel_12/rtl/verilog/
64	* empty log message *	mohor	7818d 17h	/can/tags/rel_12/rtl/verilog/
62	can_cs signal used for generation of the cs.	mohor	7824d 15h	/can/tags/rel_12/rtl/verilog/
61	Bidirectional port_0_i changed to port_0_io. input cs_can changed to cs_can_i.	mohor	7827d 04h	/can/tags/rel_12/rtl/verilog/
60	rd_i and wr_i are active high signals. If 8051 is connected, these two signals need to be negated one level higher.	mohor	7827d 06h	/can/tags/rel_12/rtl/verilog/
59	8051 interface added (besides WISHBONE interface). Selection is made in can_defines.v file.	mohor	7827d 06h	/can/tags/rel_12/rtl/verilog/
58	timescale.v is used for simulation only.	mohor	7827d 18h	/can/tags/rel_12/rtl/verilog/
57	Mux used for clkout to avoid "gated clocks warning".	mohor	7827d 18h	/can/tags/rel_12/rtl/verilog/
56	Doubled declarations removed.	mohor	7828d 17h	/can/tags/rel_12/rtl/verilog/
55	wire declaration added.	mohor	7828d 17h	/can/tags/rel_12/rtl/verilog/
52	tx_o is now tristated signal. tx_oen and tx_o combined together.	mohor	7833d 19h	/can/tags/rel_12/rtl/verilog/
51	Xilinx RAM added.	mohor	7833d 19h	/can/tags/rel_12/rtl/verilog/
50	Top level signal names changed.	mohor	7833d 19h	/can/tags/rel_12/rtl/verilog/
48	Actel APA ram supported.	mohor	7837d 11h	/can/tags/rel_12/rtl/verilog/
47	Data is latched on read.	mohor	7837d 12h	/can/tags/rel_12/rtl/verilog/
45	When a dominant bit was detected at the third bit of the intermission and node had a message to transmit, bit_stuff error could occur. Fixed.	mohor	7847d 10h	/can/tags/rel_12/rtl/verilog/

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[/] [can/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 82

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