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[/] [can/] [tags/] [rel_16/] [rtl/] - Rev 163

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Rev	Log message	Author	Age	Path
161	New directory structure.	root	5603d 08h	/can/tags/rel_16/rtl/
122	This commit was manufactured by cvs2svn to create tag 'rel_16'.		7622d 21h	/can/tags/rel_16/rtl/
121	When detecting bus-free, signal bus_free_cnt_en was cleared to zero although the last sampled bit was zero instead of one.	mohor	7622d 21h	/can/tags/rel_16/rtl/
118	Artisan RAM fixed (when not using BIST).	mohor	7631d 18h	/can/tags/rel_16/rtl/
117	Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need to be joined together on higher level.	mohor	7631d 18h	/can/tags/rel_16/rtl/
115	Artisan ram instances added.	simons	7637d 12h	/can/tags/rel_16/rtl/
112	Tx and rx length are limited to 8 bytes regardless to the DLC value.	tadejm	7664d 12h	/can/tags/rel_16/rtl/
111	Fixed according to the linter. Case statement for data_out joined.	mohor	7666d 12h	/can/tags/rel_16/rtl/
110	Fixed according to the linter.	mohor	7666d 13h	/can/tags/rel_16/rtl/
109	Fixed according to the linter.	mohor	7666d 14h	/can/tags/rel_16/rtl/
108	Fixed according to the linter.	mohor	7666d 14h	/can/tags/rel_16/rtl/
107	Fixed according to the linter.	mohor	7666d 14h	/can/tags/rel_16/rtl/
106	Unused signal removed.	mohor	7672d 12h	/can/tags/rel_16/rtl/
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7673d 02h	/can/tags/rel_16/rtl/
102	Little fixes (to fix warnings).	mohor	7675d 16h	/can/tags/rel_16/rtl/
100	Synchronization changed.	mohor	7679d 18h	/can/tags/rel_16/rtl/
99	PCI_BIST replaced with CAN_BIST.	mohor	7679d 18h	/can/tags/rel_16/rtl/
97	Overrun fifo implemented with FFs, because it is not possible to create such a memory.	simons	7685d 06h	/can/tags/rel_16/rtl/
95	Virtual silicon ram instances added.	simons	7685d 07h	/can/tags/rel_16/rtl/
93	synthesis full_case parallel_case fixed.	mohor	7690d 18h	/can/tags/rel_16/rtl/
92	clkout is clk/2 after the reset.	mohor	7691d 02h	/can/tags/rel_16/rtl/
90	paralel_case and full_case compiler directives added to case statements.	mohor	7691d 15h	/can/tags/rel_16/rtl/
88	Previous change removed. When resynchronization occurs we go to seg1 stage. sync stage does not cause another start of seg1 stage.	mohor	7692d 13h	/can/tags/rel_16/rtl/
87	When hard_sync or resync occure we need to go to seg1 segment. Going to sync segment is in that case blocked.	mohor	7692d 13h	/can/tags/rel_16/rtl/
85	Typo fixed.	mohor	7694d 05h	/can/tags/rel_16/rtl/
84	clk_cnt reduced from [8:0] to [6:0].	mohor	7695d 12h	/can/tags/rel_16/rtl/
82	Removed few signals.	mohor	7695d 13h	/can/tags/rel_16/rtl/
81	"chip select" signal cs_can_i is used only when not using WISHBONE interface.	mohor	7695d 13h	/can/tags/rel_16/rtl/
80	Form error was detected when stuff bit occured at the end of crc.	mohor	7695d 13h	/can/tags/rel_16/rtl/
79	Bit stuffing corrected when stuffing comes at the end of the crc.	tadejm	7696d 13h	/can/tags/rel_16/rtl/

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[/] [can/] [tags/] [rel_16/] [rtl/] - Rev 163

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