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Rev Log message Author Age Path
161 New directory structure. root 5647d 23h /can/tags/rel_18/
128 This commit was manufactured by cvs2svn to create tag 'rel_18'. 7634d 22h /tags/rel_18/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7634d 22h /trunk/
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7635d 18h /trunk/
125 Synchronization changed, error counters fixed. mohor 7640d 00h /trunk/
124 ALTERA_RAM supported. mohor 7660d 06h /trunk/
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7667d 12h /trunk/
119 Artisan RAMs added. mohor 7676d 09h /trunk/
118 Artisan RAM fixed (when not using BIST). mohor 7676d 09h /trunk/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7676d 09h /trunk/
115 Artisan ram instances added. simons 7682d 03h /trunk/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7709d 03h /trunk/
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7711d 03h /trunk/
110 Fixed according to the linter. mohor 7711d 04h /trunk/
109 Fixed according to the linter. mohor 7711d 05h /trunk/
108 Fixed according to the linter. mohor 7711d 05h /trunk/
107 Fixed according to the linter. mohor 7711d 05h /trunk/
106 Unused signal removed. mohor 7717d 03h /trunk/
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7717d 17h /trunk/
102 Little fixes (to fix warnings). mohor 7720d 07h /trunk/
100 Synchronization changed. mohor 7724d 09h /trunk/
99 PCI_BIST replaced with CAN_BIST. mohor 7724d 09h /trunk/
97 Overrun fifo implemented with FFs, because it is not possible to create such a memory. simons 7729d 20h /trunk/
95 Virtual silicon ram instances added. simons 7729d 22h /trunk/
93 synthesis full_case parallel_case fixed. mohor 7735d 09h /trunk/
92 clkout is clk/2 after the reset. mohor 7735d 17h /trunk/
90 paralel_case and full_case compiler directives added to case statements. mohor 7736d 06h /trunk/
88 Previous change removed. When resynchronization occurs we go to seg1
stage. sync stage does not cause another start of seg1 stage.		 mohor 7737d 04h /trunk/
87 When hard_sync or resync occure we need to go to seg1 segment. Going to
sync segment is in that case blocked.		 mohor 7737d 04h /trunk/
85 Typo fixed. mohor 7738d 20h /trunk/

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