OpenCores
URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [rel_20/] - Rev 139

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
139 Signal bus_off_on added. igorm 7450d 12h /can/tags/rel_20/
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7489d 14h /can/tags/rel_20/
137 Header changed. mohor 7489d 14h /can/tags/rel_20/
136 Error counters changed. mohor 7489d 15h /can/tags/rel_20/
135 Header changed. mohor 7489d 15h /can/tags/rel_20/
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.		 mohor 7597d 12h /can/tags/rel_20/
130 mbist signals updated according to newest convention markom 7603d 23h /can/tags/rel_20/
129 Error counters changed. mohor 7620d 08h /can/tags/rel_20/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7620d 08h /can/tags/rel_20/
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7621d 04h /can/tags/rel_20/
125 Synchronization changed, error counters fixed. mohor 7625d 10h /can/tags/rel_20/
124 ALTERA_RAM supported. mohor 7645d 16h /can/tags/rel_20/
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7652d 22h /can/tags/rel_20/
119 Artisan RAMs added. mohor 7661d 19h /can/tags/rel_20/
118 Artisan RAM fixed (when not using BIST). mohor 7661d 19h /can/tags/rel_20/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7661d 19h /can/tags/rel_20/
115 Artisan ram instances added. simons 7667d 13h /can/tags/rel_20/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7694d 14h /can/tags/rel_20/
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7696d 14h /can/tags/rel_20/
110 Fixed according to the linter. mohor 7696d 14h /can/tags/rel_20/
109 Fixed according to the linter. mohor 7696d 15h /can/tags/rel_20/
108 Fixed according to the linter. mohor 7696d 15h /can/tags/rel_20/
107 Fixed according to the linter. mohor 7696d 16h /can/tags/rel_20/
106 Unused signal removed. mohor 7702d 13h /can/tags/rel_20/
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7703d 03h /can/tags/rel_20/
102 Little fixes (to fix warnings). mohor 7705d 18h /can/tags/rel_20/
100 Synchronization changed. mohor 7709d 19h /can/tags/rel_20/
99 PCI_BIST replaced with CAN_BIST. mohor 7709d 19h /can/tags/rel_20/
97 Overrun fifo implemented with FFs, because it is not possible to create such a memory. simons 7715d 07h /can/tags/rel_20/
95 Virtual silicon ram instances added. simons 7715d 08h /can/tags/rel_20/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.