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Rev Log message Author Age Path
161 New directory structure. root 5599d 15h /can/tags/rel_20/
142 This commit was manufactured by cvs2svn to create tag 'rel_20'. 7361d 18h /tags/rel_20/
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7361d 18h /trunk/
140 I forgot to thange one signal name. igorm 7416d 17h /trunk/
139 Signal bus_off_on added. igorm 7416d 17h /trunk/
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7455d 20h /trunk/
137 Header changed. mohor 7455d 20h /trunk/
136 Error counters changed. mohor 7455d 20h /trunk/
135 Header changed. mohor 7455d 20h /trunk/
134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.		 mohor 7563d 18h /trunk/
130 mbist signals updated according to newest convention markom 7570d 05h /trunk/
129 Error counters changed. mohor 7586d 13h /trunk/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7586d 14h /trunk/
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7587d 10h /trunk/
125 Synchronization changed, error counters fixed. mohor 7591d 16h /trunk/
124 ALTERA_RAM supported. mohor 7611d 22h /trunk/
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7619d 03h /trunk/
119 Artisan RAMs added. mohor 7628d 00h /trunk/
118 Artisan RAM fixed (when not using BIST). mohor 7628d 00h /trunk/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7628d 00h /trunk/
115 Artisan ram instances added. simons 7633d 18h /trunk/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7660d 19h /trunk/
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7662d 19h /trunk/
110 Fixed according to the linter. mohor 7662d 19h /trunk/
109 Fixed according to the linter. mohor 7662d 20h /trunk/
108 Fixed according to the linter. mohor 7662d 21h /trunk/
107 Fixed according to the linter. mohor 7662d 21h /trunk/
106 Unused signal removed. mohor 7668d 19h /trunk/
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7669d 08h /trunk/
102 Little fixes (to fix warnings). mohor 7671d 23h /trunk/

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